A 1.6-to-3.0-GHz Fractional-${N}$  MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

Santiccioli, Alessio; Mercandelli, Mario; Lacaita, A.L.; Samori, Carlo; Levantino, Salvatore

doi:10.1109/jssc.2019.2941259

Cited by 30 publications

(11 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Fig. 23, the proposed architecture achieves a significant improvement in FoM NORM [15] compared to state-of-the-art synthesizers.…”

Section: Resultsmentioning

confidence: 91%

“…In addition to the constant-slope method, several other approaches were reported to improve DTC linearity. For instance, in [15], both edges of the feedback clock were used to reduce the required DTC range by half, while background nonlinearity calibration techniques were explored in [9]. Other methods include adding redundancy in the DTC and randomizing the INL errors to make them appear as white noise [16].…”

Section: Brief Overview Of Ro-based Synthesizersmentioning

confidence: 99%

See 1 more Smart Citation

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

Elmallah

Zhu

Khashaba

et al. 2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digitalto-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC's linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.

show abstract

“…As shown in Fig. 23, the proposed architecture achieves a significant improvement in FoM NORM [15] compared to state-of-the-art synthesizers.…”

Section: Resultsmentioning

confidence: 91%

Section: Brief Overview Of Ro-based Synthesizersmentioning

confidence: 99%

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

Elmallah

Zhu

Khashaba

et al. 2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…Using a BBPD is advantageous for reducing quantization error compared with the conventional multibit time-to-digital (TDC) with limited time resolution. Prior works [3]- [6], [9], [11] have denoted that this architecture has the potential to achieve excellent noise performance and power efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…This model provides a general analysis framework to predict output noise, where the z-domain functions support extensive behavior simulations. It can be adopted to a BBPD loop, but the closed-loop filtering to the injected DCO noise is neglected in [6]. [10] and [14] analyze the realigned oscillator from the time-domain observation.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

Shi

2022

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted inputreferred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations.

show abstract

“…However, the reference and the voltage control delay line (VCDL) secondary jitter have been ignored in these papers. There are great methods for improving jitter in Gholami et al, 15‐21 but they did not present a mathematical analysis. In this work, a delay error equation is presented that is more accurate than previous works.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a low jitter delay‐locked loop using lock state detector

Modanlou

Ardeshir

Gholami

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V.

show abstract

A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

Cited by 30 publications

References 18 publications

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

Analysis and design of a low jitter delay‐locked loop using lock state detector

Contact Info

Product

Resources

About

A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

Cited by 30 publications

References 18 publications

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

Analysis and design of a low jitter delay‐locked loop using lock state detector

Contact Info

Product

Resources

About

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer