Summary
In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V.
In this article, a new technique for reducing second-order and third-order intermodulation (IM2 and IM3) for an output current of the subharmonic mixer is presented. First, to reduce second-order and third-order of the Volterra's kernel, IM2 current injection technique has been used. By the auxiliary path, the IM2 current which has been generated in the doubler with the phase difference of 180°relative to inherent IM2 of the output is injected into the output node.Also, this produced IM2 in the frequency doubler has been injected into the circuit by another auxiliary path, so that, in the output, an IM3 with opposite phase of inherent IM3 of the output mixer's current is presented. Besides, to easier design, the Volterra series expansion is used and equations related to Volterra kernels of the output current are extracted. Furthermore, the noise of the auxiliary path transistors connected to the output can be neglected because of the small g m of their transistors compared to the main path. The results of simulations by ADS simulator in 0.18-μm TSMC technology show that the proposed technique has simultaneously improved the values of IIP3 and IIP2 up to 21 and 92 dBm, compared to conventional subharmonic mixers.
KEYWORDSGilbert cell mixer, subharmonic mixer, high linearity, second-order and third-order input intercept point (IIP2, IIP3), second-order and third-order intermodulation (IM2, IM3)
SummaryIn this article, an injection‐locked frequency divider (ILFD) is presented. By assuming the maximum phase of the tank current, we obtain a relation for the lock range. Besides, the effects of parasitic capacitors on the lock range have been probed. The analysis shows that the greater the phase difference between the tail current and injected signal, the phase of the tank current increases and, consequently, the lock range also increases. The accomplished simulations confirm the correct performance of the proposed design and the extracted relationships. The simulations have been CMOS technology and with a 0.9‐V supply voltage. The results show that the current consumption equals 3.7 mA and the power consumption equals 3.33 mW. The proposed ILFD lock range with phase shift technique with power input signal 0 dBm is equal to 5.1 GHz (3.6–8.7 GHz), and the relative percentage of the lock range is also 83%.
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