A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness [l]. This is mainly limited by the information loss induced by the higher gate leakage current after cycling[2], becoming critical below 1 0 m thickness. Multiple trap assisted tunneling has been proposed to model the conduction of degraded thick oxides[3], but it is not yet clear the nature of the associated defects.Data here reported are obtained on flat area capacitors with a standard full CMOS process with STI (Shallow Trench Isolation) and dual-gate technology. Tunnel oxides of 8nm thickness have been grown with different oxidation technologies. The measurement procedure is based on three steps [4] to estimate the stable charge (QstSb;J and its position [5] and the stationary SILC measured at a fixed field and extrapolated by the tunneling front model [6,7].The post oxidation treatment impacts SlLC and trapped charge and a linear correlation between SILC and bulk negative trapped charge is found (fig. I). SILC is generally associated with neutral bulk traps[3], allowing a trap assisted tunneling through the oxide. These neutral traps are created by a two-step process of anode injected hole trapping and subsequent recombination with electrons [8,9], as shown by the behavior of V(t) curve at the tum around during constant current stress. The ohsmed correlation between negative trapped charge and SlLC can be interpreted as due to the same trap, which is positively charged at low fields during SILC measurement, while it is negatively charged at the higher field used to determine the bulk trapped charge. 186-12 , I Figure 1: SUC measured at -5.3 MVIcm YS. QsmbS. with different postoxidation lreatments (at fixed t. , = 8 nm).To verify if the same trap is involved, the kinetics of the defect annealing has been carried out at different temperatures between 5 0 T and 250°C. As reported in fig. 2, SILC is indeed observed to decrease with the annealing time. In order to have a significant SILC without reaching the F-N conduction, a standard measure at -5V has been chosen. In fig. 3 the value of SlLC normalized for the SILC right afler stress is reported versus the annealing time at different temperatures. Increasing the temperature over 150°C a much stronger annealing efficiency is found. The same effect is also observed for the fixed trapped charge ( fig. 4). Both phenomena have activation energy of l.leV, similar to the Si-Si bond energy. A strong correlation between SILC and Q.a,e is found ( fig. 5): this fully confirms that the same defect is indeed responsible for the two phenomena.
The scaling down of Flash memories can be pursued using theconventional stacked gate architecture only with major changesof the active dielectrics, mainly the inter-poly dielectric(IPD).The required 4-6 nm EOT thickness for the IPD cannot beachieved by the conventional ONO (Oxide-Nitride-Oxide)technology which starts failing in the 10-12 nm range in termsof charge retention properties. Therefore high-k materials arecurrently investigated for IPD formation in future Flashmemories. It is worth noticing that the requirements for IPD arevery different from those of the gate dielectrics used inlogics. Alumina and alumina based materials (like hafniumaluminates) are among the possible candidates. Promising andtunable electrical and structural properties are achieved forthese materials by varying the high-k stack chemicalcompositions and post- deposition thermal treatments. Differentmaterial combinations have been selected as potential solutionsfor the replacement of the conventional ONO(Oxide-Nitride-Oxide) stack
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