Combined Nanoscale and Device-Level Degradation Analysis of $\hbox{SiO}_{2}$ Layers of MOS Nonvolatile Memory Devices

Lanza, Mario; Porti, M.; Nafría, M.; Aymerich, X.; Sebastiani, Alessandro; Ghidini, G.; Vedda, A.; Fasoli, M.

doi:10.1109/tdmr.2009.2027228

Cited by 14 publications

(11 citation statements)

References 19 publications

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“…The most common techniques used for TMO deposition are atomic layer deposition (ALD) [66] and sputtering. The most common techniques used for TMO deposition are atomic layer deposition (ALD) [66] and sputtering.…”

Section: Deposition Of the Rs Mediummentioning

confidence: 99%

“…[3,7] To do so, after inducing the set/reset transition (either by an I-V sweep or a PVS) the state retention can be studied by applying a constant voltage stress (CVS) over time using a low (≈0.1 V) read voltage, and subsequently measuring a current versus time (I-t) curve for each resistive state. [22] For example, in CF based RS devices, a larger CL during the set I-V sweep produces a larger CF that is more stable over the time, [122,123] which will enlarge the state retention time detected in the subsequent I-t curve. Normally the challenging point is to keep a long retention time in LRS, as the atomic rearrangements introduced during the set stress may vanish over the time.…”

Section: State Retentionmentioning

confidence: 99%

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Recommended Methods to Study Resistive Switching Devices

Lanza

Wong

Pop

et al. 2018

Adv Elect Materials

496

434

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Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.

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Section: Deposition Of the Rs Mediummentioning

confidence: 99%

Section: State Retentionmentioning

confidence: 99%

Recommended Methods to Study Resistive Switching Devices

Lanza

Wong

Pop

et al. 2018

Adv Elect Materials

496

434

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“…In its origin CAFM, was mainly used to characterize the electrical properties of thin (<50 nm) dielectric materials (i.e., SiO 2 , HfO 2 , Al 2 O 3 ) at nanoscale. More specifically, the CAFM can be used to study tunneling current, polycrystallization, charge trapping and de‐trapping, random telegraph noise, stress induced leakage current (SILC), dielectric breakdown, and resistive switching . Recently, its use has also expanded to other low‐dimensional materials, such as nanowires (NWs), carbon nanotubes (CNT), nanodots, and 2D materials .…”

Section: Introductionmentioning

confidence: 99%

Emerging Scanning Probe–Based Setups for Advanced Nanoelectronic Research

Hui

Wen

Chen

et al. 2019

Adv Funct Materials

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Figure 3. a) Schematic of the CAFM integrated into the SEM. b) SEM image of a CAFM tip landed on the NW arrays. c) Top-view SEM image of the ZnO NW arrays. d) AFM topographic map of the as-fabricated ZnO NW arrays collected in tapping mode using a Si tip. Reproduced with permission. [109] Despite the main drawback of this method is the instability of the filament due to the extreme thinness of the lamella, one work proved a stable cyclic operation (more than 60 switching cycles) in 30 nm CuTe-based conductive bridging random access memory (CBRAM). [119] Multiprobe Advanced Characterization MethodsDespite the high lateral resolution of SPM represents a very strong advantage compared to traditional electrical characterization methods (i.e., probe station), the use of only one probe Adv. Funct. Mater. 2020, 30, 1902776Figure 4. a) TEM image of an overview of a sample; each finger contains a stack of Ni/HfO 2 /SiO x /n + Si. Current-time plots indicate the typical b) SET and c) RESET processes. d) TEM image (top) and corresponding EDS nickel map (bottom) of the device in a SET state. Reproduced with permission. [114] Copyright 2015, Wiley VCH. e) I-V graph of in situ electroforming and RESET of Pt/ZnO/Pt where the top electrode (TE) was negatively biased while the bottom electrode (BE) was grounded, and corresponding f-h) electroforming and i,j) RESET images extracted. Reproduced with permission. [118]

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“…the nanoscale gate oxide properties [13]. The combination of both analyses is specially difficult because once the device is stressed and its electrical properties are analyzed, the structure under investigation must be deprocessed to expose the gate oxide to the CAFM tip.…”

mentioning

confidence: 99%

“…Such experimental difficulties are specially remarkable in the case of MOSFETs. As a consequence, the few studies performed in this direction have been focussed on MOS capacitors and, therefore, these works are restricted to stresses that are uniform over the gate active area [13] such as BTI. In this paper, the nanoscale electrical properties of the gate oxide of MOSFETs after homogeneous (BTI) and nonhomogeneous (CHC) device level stresses have been studied with CAFM.…”

mentioning

confidence: 99%

A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

Bayerl

Porti

et al. 2014

IEEE Trans. Electron Devices

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This paper addresses the impact of different electrical stresses on nanoscale electrical properties of the MOSFET gate dielectric. Using a conductive atomic force microscope (CAFM) for the first time, the gate oxide has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses. The CAFM explicitly shows that while the degradation induced along the channel by a negative BTI stress is homogeneous, after a CHC stress different degradation levels can be distinguished, being higher close to source and drain.Index Terms-Atomic force microscopy (AFM), channel hot-carrier (CHC) degradation, MOSFET, negative bias temperature instability (NBTI).

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Combined Nanoscale and Device-Level Degradation Analysis of $\hbox{SiO}_{2}$ Layers of MOS Nonvolatile Memory Devices

Cited by 14 publications

References 19 publications

Recommended Methods to Study Resistive Switching Devices

Recommended Methods to Study Resistive Switching Devices

Emerging Scanning Probe–Based Setups for Advanced Nanoelectronic Research

A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

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