Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and timeconsuming data movement that plagues current designs. Here we review the development of inmemory computing using resistive switching devices, where the two-terminal structure of the devices and the direct data processing in the memory can enable area-and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing.

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~10 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

No abstract

No abstract

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

No abstract

Ultrathin two-dimensional (2D) semiconducting layered materials offer a great potential to extend the Moore's Law (1). One key challenge for 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. The insulating van der Waals layer, hexagonal boron nitride (hBN), is an excellent interface dielectric to 2D semiconductors, efficiently reducing charge scatterings (2, 3). Recent studies have shown the growth of single-crystal hBN films on molten Au surfaces (4) or bulk Cu foils (5). However, using molten Au is not favored in industry due to high cost, cross-contamination, and potential issues of process control and scalability. Cu foils may be suitable for roll-to-roll processes, but unlikely to be compatible with advanced microelectronic fabrication on Si wafers. Thus, only a reliable approach to grow single-crystal hBN on wafers can help realize the broad adoption of 2D layered materials in industry. Previous efforts on growing hBN triangular monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when they merge as films (6,7). Growing singlecrystal hBN on such a high-symmetry surface planes (5,8) is commonly believed to be impossible even in theory. In stark contrast, we have successfully realized the epitaxial growth of single-crystal hBN monolayers on a Cu ( 111) thin film across a 2-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxy to the underlying Cu lattice is enhanced by the lateral docking to Cu (111) steps, to ensure the mono-orientation of hBN monolayers. The obtained singlecrystal hBN, incorporated as an interface layer between MoS2 and HfO2 in a bottom-gate configuration, has enhanced the electrical performance of transistors based on monolayer MoS2. This reliable approach of producing wafer-scale single-crystal hBN truly paves the way for developing futuristic 2D electronics.First, a single-crystal Cu (111) thin film on a wafer is needed. Single-crystal Cu in thick foils can be achieved through recrystallization induced by implanted seeds (5,9). However, for the formation of Cu (111) thin film on a wafer, the crystallinity strongly relies on the underlying substrate lattices. Here we used a c-plane sapphire as the substrate, on which a 500-nm-thick polycrystalline Cu film was sputtered followed by extensive thermal annealing to achieve singlecrystal Cu (111) films (10). One challenge is that Cu (111) tends to form twin grains separated by twin grain boundaries, through kinetic growth processes. Fig. 1a illustrates the atomic arrangements for the typical twinned Cu (111) structure. We find that the post-annealing at a high temperature (1,040 -1,070 °C) in the presence of hydrogen is the key to removing the twin grains, consistent with recent reports (10,11). Figures 1b and 1c show the optical micrographs (OMs) and electron backscatter diffraction (EBSD) patterns for the Cu (111) thin films after annealing at 1,000 °...

No abstract