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Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology from one generation to the next. In this paper, the impact of CMOS technology scaling on the performance of domino CMOS logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper.A technique that extends the life time of domino logic in spite of CMOS technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 µm technology with power-supply voltage, V DD =1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area penalty.

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During the reading process of one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier. The net result is that the higher voltage will rise to V DD while the lower one will decrease to 0 V. Simulation results for the 0.13 mm CMOS technology with V DD = 1.2 V reveal that approximately 40% of the read access time is associated with the sense amplifier operation in addition to the area required by each sense amplifier for each column in the memory array. In this paper, a novel readout technique for use with DRAM cells will be presented. This method depends on using an initially charged capacitance, then deciding whether to keep it charged or discharge it according to the stored data. Simulation results show that approximately 20% of the read access time is saved for the case of "1" storage which represents the worst case. The average power of the conventional scheme in case of stored "1" or "0" is 18.5 mW. The corresponding values for the proposed scheme are 9.8 mW and 2.25 mW. The significant reduction of the power consumption can be attributed to the reduction of the voltage swing of the bitline parasitic capacitance and taking the output data at a much smaller capacitance. The powerdelay products (PDPs) for the conventional and proposed readout schemes assuming the worst case (stored "1") are 388.5 fJ and 166.6 fJ, respectively.Dynamische RAM-Speicher ohne Leseverstä rker.Wä hrend des Leseprozesses von dynamischen Ein-Transistor-/Ein-Kondensator-DRAM-Speicherzellen (1T-1C DRAM) ist es notwendig, eine kleine Spannungsdifferenz (im Bereich von 30 mV bis 100 mV) mit einem entsprechenden Leseverstä rker zu verstä rken. Daraus resultierend wä chst die hö here Spannung zu V DD an, wä hrend die niedrigere Spannung auf 0 V sinkt.Die Simulationsergebnisse fü r die 0,13 mm CMOS-Technologie mit V DD = 1,2 V zeigen, dass ungefä hr 40 % der Lesezugriffszeit dem Leseverstä rker zugeordnet werden kann -zusä tzlich zur benö tigten Siliziumflä che der Leseverstä rker fü r jede Spalte im Speicherbereich. In der vorliegenden Arbeit wird eine neuartige Auslesetechnik fü r die Verwendung von DRAM-Zellen prä sentiert. Diese Methode basiert auf einer anfä nglich geladenen Kapazitä t und der dann folgenden Entscheidung, ob sie entsprechend der gespeicherten Daten geladen bleiben oder wieder entladen werden soll. Die Simulationsergebnisse zeigen, dass ungefä hr 20 % der Lesezugriffszeit im Fall einer "1"-Speicherung, die den schlechtesten Fall darstellt, eingespart werden kö nnen. Die durchschnittliche Leistung der konventionellen Regelung im Fall einer "1"-oder "0"-Speicherung beträ gt 18,5 mW. Die entsprechenden Werte fü r die vorgeschlagene Regelung lauten 9,8 mW und 2,25 mW. Die signifikante Verringerung des Stromverbrauchs kann der Reduzierung des Spannungshubs an der BitlineKapazitä t und der Tatsache, dass die Ausgabedaten an einer wesentlich geringeren Kapazitä t abgegriffen werden, zugeschrieben...