Dynamic random-access memories without sense amplifiers

Sharroush, Sherif M.; Abdalla, Yasser S.; Dessouki, Ahmed A. S.; El-Badawy, El-Sayed A.

doi:10.1007/s00502-012-0083-3

Cited by 10 publications

(3 citation statements)

References 2 publications

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“…Our goal is to design a new DRAM architecture that provides low latency for the common case while still retaining a low cost-per-bit overall. Our proposal, which we call TieredLatency DRAM, is based on the key observation that long bitlines are the dominant source of DRAM latency [47].…”

Section: Introductionmentioning

confidence: 99%

Tiered-latency DRAM: A low latency and low cost DRAM architecture

Lee

Kim

Seshadri

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-o made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-ampli er through a wire called a bitline. These bitlines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater senseampli er area overhead. In this work, we introduce TieredLatency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-e ciency for both single-core and multi-programmed workloads.

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Section: Introductionmentioning

confidence: 99%

Tiered-latency DRAM: A low latency and low cost DRAM architecture

Lee

Kim

Seshadri

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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“…The reason for the slow latency improvement is directly related to cost and power consumption [16,17]. In order to reduce the sensing and pre-charge time, for example, the number of cells connected per bit-line should be reduced [18]. However, this leads to an increase in the number of bit-line sense amplifiers, and thus increases the chip size.…”

Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Shin

Chung

2019

Micromachines

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Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.

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“…Although the cell and the bitline must be restored to their quiescent voltages during and after an access to a cell, such a procedure takes much longer when the parasitic capacitance of the bitline is large. Due to these two reasons, and based on a detailed latency breakdown discussed in Section 3.1 of our HPCA 2013 paper [73], we conclude that long bitlines are the dominant source of DRAM latency [44,72,73,90,91,122].…”

Section: Key Observations and Our Goalmentioning

confidence: 99%

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

Lee¹,

Kim²,

Seshadri³

et al. 2018

Preprint

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Dynamic random-access memories without sense amplifiers

Cited by 10 publications

References 2 publications

Tiered-latency DRAM: A low latency and low cost DRAM architecture

Tiered-latency DRAM: A low latency and low cost DRAM architecture

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

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