Impact of technology scaling on the performance of domino CMOS logic

Abstract

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology from one generation to the next. In this paper, the impact of CMOS technology scaling on the performance of domino CMOS logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper.A technique that extends the life time of domino logic in spite of CMOS technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 µm technology with power-supply voltage, V DD =1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area penalty.

FDSTDL: Low‐power technique for FinFET domino circuits

“…If n no. of identical fins are connected in parallel, the effective channel width is given by The effective length of the channel in FinFET is given by where L gw is the length of the gate covering the fin and L finext is the length of the fin on two sides connecting source and drain.…”

“…To reduce various components of power consumption, device dimensions and supply voltages are scaled down. Scaling of devices leads to an increase in leakage currents due to unwanted short channel effects . These short channel effects can be reduced by using multi‐gate field‐effect transistor (FET) .…”

“…Scaling of devices leads to an increase in leakage currents due to unwanted short channel effects. 6 These short channel effects can be reduced by using multi-gate field-effect transistor (FET). [7][8][9] This multi-gate FET is termed as fin fieldeffect transistor (FinFET).…”

“…If n no. of identical fins are connected in parallel, the effective channel width is given by 6 W eff ¼ n: 2H fin þ t si ð Þ :…”

Ultra low-power asynchronous-logic design for high variation-space and wide operation-space applications

“…With this keeper, the previous 'floating' node for an output of logic '1' is now 'statically' held by the PMOS transistor. However, by adding the keeper, a current contention problem similar to the pseudo-NMOS logic delineated earlier is inadvertently created when the PDN is switched on (to produce an output '0')[51]. As in pseudo-NMOS logic, the PMOS keeper is thus needed to be sized small as compared to the PDN.Unfortunately, as delineated earlier, this solution is largely unsatisfactory in sub-V t because the circuit operation is unreliable due to process variations that may alter the relative strengths of the transistors therein.In summary, amongst the four reviewed digital logic families, the static logic and the pass transistor/transmission gate logic do not suffer the current contention problem of their pseudo-NMOS and dynamic (with keeper) logic counterparts.…”