SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology

Garg, Sandeep; Gupta, Tarun Kumar

doi:10.1007/s10825-020-01499-1

Cited by 5 publications

(2 citation statements)

References 31 publications

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“…Depending on the fin height and fin thickness, a FinFETs effective width might vary. The Fin-FETs used have a gate length of 18nm and a fin pitch of 48nm [2]. A CPU's adder circuit is largely responsible for its speed performance.…”

Section: Introductionmentioning

confidence: 99%

“…The SUM generated by HA0 and Ex1_0 adder is given to 2-1M _1 which produces S[0] and then CARRY generated by HA0 and Ex1_0 is given to 2-1M_2 which produces C[0].In this PCSA the Carry propagation is done through The generated C[0] is propagated through 2-1M_3 which provides S[1] as output with respect to Cin (0 or 1). Similarly, S[2], S[3], and C[1], C[2], Cout are generated. (i) CMOS Excess-1 adder using 2-1M (ii) TGL Excess-1 adder using 2-1M…”

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confidence: 99%

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A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

Battini,

Kosaraju

2024

Semicond. Sci. Technol.

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To choose the option between an excess-1 result and a normal result,the conventional carry select adder (CCSA) employs two ripple-carry adders and amultiplexer in the last step. Second, whereas the proposed single-stage carry selectadder (SSCSA) avoids using full adders for the generation of both normal and excessresults, the present full adders require multiple full adders. A novel architecture isdeveloped and specifically designed to improve power dissipation and latency. It relieson a single circuit that produces normal/excess-1 results dependent on input carry.Heterogeneous logic combining CMOS, Dual Value Logic (DVAL), and TransmissionGate Logic (TRGL) with 22nm Fin-FETs powers the 1-bit SSCSA circuit. Bettercircuit regularity is displayed by the 4-bit SSCSA as it only uses one type of 1-bitSSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22nm FinFETtechnology, all adders, including 4- and 8-bit adders, are designed, simulated, andexamined. According to the resulting study, the 4-bit SSCSA outperforms the bestadder currently in use in terms of speed performance and power dissipation by 17.6%and 27.6%, respectively. By comparison with all other designs, SSCSAs outperformthem at each and every corner.

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Speed and Power Tradeoff Based on FinFET Structure, Voltage Changing and Circuit Layout

Chen

Yang

2022

2022 IEEE 5th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE)

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SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology

Cited by 5 publications

References 31 publications

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

Speed and Power Tradeoff Based on FinFET Structure, Voltage Changing and Circuit Layout

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