On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI PMOS current degradations across process, temperature, and varying activity factors. We show that a set of 1000 such small sensors can predict chip lifetime to an uncertainty of 7% to 10%. We also show that, once the total area dedicated to sensing is chosen, the lifetime prediction uncertainty is almost insensitive to the tradeoff between the number of sensors and the area of each individual sensor.
In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar array based molecular memory, and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, we discuss reading and writing such memory using CMOS and compiling a solution for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
No abstract
This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for an FPNI implementation using 90 nm CMOS with 15 nm wide nanowire interconnects. Detailed simulations of this design illustrate that critical design choices and tradeoffs exist beyond those specified by the architecture. This includes the selection of the types of junction nanodevices, as well as the implementation of low-level circuits. In particular, the simulation results presented here show that only nanodevices with an 'on/off' current ratio of 200 or more are suitable to produce correct system-level behaviour. Furthermore, the design of the CMOS logic gates in the FPNI system must be customized to accommodate the resistances of both 'on'-state and 'off'-state nanodevices. Using these customized designs together with models of suitable nanodevices, additional simulations demonstrate that, relative to conventional 90 nm CMOS FPGA systems, performance gains can be obtained of up to 70% greater speed or up to a ninefold reduction in energy consumption.
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