Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay

Abstract

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI PMOS current degradations across process, temperature, and varying activity factors. We show that a set of 1000 such small sensors can predict chip lifetime to an uncertainty of 7% to 10%. We also show that, once the total area dedicated to sensing is chosen, the lifetime prediction uncertainty is almost insensitive to the tradeoff between the number of sensors and the area of each individual sensor.

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

“…Simulation results in Section IV take those non-idealities into account, derive design guidelines to maximize PRTA benefits, and demonstrate that PRTA is highly beneficial for systems that experience workload with low stress probability characteristics. Real-time aging information for PRTA can be obtained (or calibrated) from a variety of sources: 1) on-chip ring oscillators or other canary equivalent circuits [27]- [32]; 2) on-chip sensors such as temperature sensors (by predicting aging based on temperature profiles and assuming worst-case workload profiles) [33]- [36]; 3) delay shift detectors [11], [21], [37]; 4) on-line self-test and self-diagnostics [38]- [40]; and 5) indirectly measuring degradation by adjusting selftuning parameters until failure occurs.…”

“…For instance, the effect of a 3 ps resolution will be less pronounced at larger nominal delays. Resolutions of the order of picoseconds (ps) or sub-picoseconds have been reported by existing techniques [11], [27]- [33]. Depending on the implementation, PRTA can introduce additional overhead in terms of power.…”

Dependable digitally-assisted mixed-signal IPs based on integrated self-test & self-calibration

“…As a result it will generate a new netlist allowing an "aged" simulation. A number of publications have appeared on reliability simulation of analogue / MS circuits [16,21,22]. This information will be used later on, in evaluating the aging behaviour of our OpAmp by circuit simulation, and conclude where counteractions have to be taken.…”

A Multi-Level Approach to NBTI Mitigation in Processors

“…However, guardbanding needs to cover the worst case from both PV and NBTI, and can lead to large area and power overhead. An alternative solution to this problem is to embed on-chip sensors to dynamically track NBTI [52,53] and use mitigation techniques to handle the problem before it manifests as system level failures. Recent efforts propose dedicated sensors for this purpose which comes with the cost of extra area or performance [52,53].…”

“…An alternative solution to this problem is to embed on-chip sensors to dynamically track NBTI [52,53] and use mitigation techniques to handle the problem before it manifests as system level failures. Recent efforts propose dedicated sensors for this purpose which comes with the cost of extra area or performance [52,53]. In order to reduce this overhead, one could investigate if power consumption of the chip (or components of the chip) changes with the degradation due to NBTI and if power could be used as a sensor for tracking NBTI.…”