A Multi-Level Approach to NBTI Mitigation in Processors

Abstract

We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: a degradation in the reliability of silicon devices. Processors have become highly susceptible to a variety of reliability problems in silicon, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques. This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the logic and memory structures in the processor that impose very little performance, power, and area overheads. This research also creates the foundation for understanding NBTI in the context of one other important processor reliability problem: process variations.

Virtually-aged sampling DMR

“…Thus it's presence can amplify the role of mitigation techniques and allow mitigation techniques to be very aggressive, since they can operate under the assumption that there is a fail-safe prediction/detection technique which guarantees no incorrect operation will occur. For example, mitigation techniques like Facelift [55], Bubblewrap [25] and others [48] can be configured to be aggressive in terms of energy efficiency.…”