Design approaches for hybrid CMOS/molecular memory based on experimental device data

Abstract

In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar array based molecular memory, and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, we discuss reading and writing such memory using CMOS and compiling a solution for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.

A Programmable Majority Logic Array Using Molecular Scale Electronics

“…It should be noted that such devices themselves are very much in an experimental stage and in many cases cannot be expected to approach ideal performance. That said, by developing device models based on actual device data, as has been done in other related works [12], [16], [17], the resulting simulations more closely reflect what can actually be expected when such circuits and architectures are fabricated.…”

“…To date, most circuit and architecture designs focus on the utilization of the hysteretic switching and memory properties common to many molecular devices [7]- [12]. As these devices can be viewed as switchable fuses, they are useful for the implementation of both memory and programmable logic.…”

Challenges to Crossbar Integration of Nanoscale Two-Terminal Symmetric Memory Devices

“…Therefore, two terminal symmetric memory devices cannot be used directly in a crossbar memory. Even worse, the grounded solution proposed in [4] does not work in this case either. To make it work, we should use a diode of switch to make the symmetric memory device behave asymmetrically.…”

Memory Select Devices

“…One example of these sneak paths is shown in Figure 12.2. The impact of the sneak paths on the reading and writing operations of crossbar arrays has been analyzed in numerous papers [6][7][8][9][10][11][12][13][14].…”