Challenges to Crossbar Integration of Nanoscale Two-Terminal Symmetric Memory Devices

Abstract

Abstract-Crossbar is the most efficient architecture to organize memory devices into dense, large-scale arrays. Emerging nanotechnology promises two-terminal, symmetric memory devices of superior electrical properties. In this work, however, we show that these two-terminal, symmetric devices impose grave challenges to the crossbar-based memory organization. First, we prove that conventional crossbar organization will not work for such symmetric devices. Second, we propose a revised crossbar organization that does work for such devices. However, diodes or switches must be employed to convert such devices into asymmetrical devices in order to avoid considerable energy cost, which can significantly discount their advantage over conventional asymmetrical devices. Third, we demonstrate that there is significant difference in delay and power consumption for accessing a memory device of different contents, i.e., 0 or 1. Such difference constitutes a performance bottleneck of crossbarbased integration of resistive memory devices.

Modelling of wire resistance effect in PCM‐based nanocrossbar memory

“…A crossbar is a memory structure that integrates memory devices (PCM cells in this paper) in large arrays, and provides efficient means to facilitate large‐scale geometry which in turn enables ultra‐high densities [4]. Crossbar structures are constructed of a mesh of intersecting rows (word lines) and columns (bit lines) of conducting wires; with memory elements placed at each intersection point as shown in Fig.…”

“…Therefore, it minimises leakage currents and related power dissipation. Along with leakage currents [4–6], memory nanocrossbar structures have multiple performance issues including stray capacitances caused by memory peripheral circuitry [7] and thermal crosstalk [8]. Moreover, connecting wire resistance [9, 10] that consume energy and can affect the programming performance.…”