Designing CMOS/molecular memories while considering device parameter variations

Abstract

In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.

Progress in rectifying-based RRAM passive crossbar array

“…One is using CMOS circuit [13] and the other is utilizing rectifying effect of RRAM passive crossbar array. When utilizing CMOS circuit, addition of at least one row of load devices to access the selected memory cells is needed.…”

Architecturally-Enforced InfoSec in a General-Purpose Self-Configurable System

“…It is thus an easy build target for contemporary CMOS, but is also likely wellsuited for newer, emerging technologies such as DNA scaffolding [13], Quantum CA [14] and Crossbar Nanocomputing [15], where huge numbers of cells could potentially be created, on 2D or 3D substrates..…”

Overview: Memristive devices, circuits and systems

“…Due to the hysteretic switching behavior, memory is one application that naturally suits memristor devices. In fact, several groups, including ours at NYU-Poly, have explored the potential for memristors in high density memory arrays [5,6]. Much of this early work has described how arrays of memristive devices at the crosspoints can be integrated with CMOS for very dense memory [6].…”

“…In fact, several groups, including ours at NYU-Poly, have explored the potential for memristors in high density memory arrays [5,6]. Much of this early work has described how arrays of memristive devices at the crosspoints can be integrated with CMOS for very dense memory [6]. Moving forward, we are beginning to investigate the prospects of multilevel memristors (consisting of several resistivity states) integrated into memory systems that hold multiple bits of data per memory cell.…”