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A single-chip GPS receiver for GSM and CDMA handsets, designed to provide location identification feature, is described in this paper. This receiver uses a low-IF RF-front-end, that includes an LNA, image rejection using IQ mixers and passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, delta-sigma ADC and a digital IF-filter. An attempt is made to minimize the number of external components and have only a single pre-select filter between the antenna and the IC. In the absence of any SAW filter, the ability of the receiver to tolerate jammers is very critical, due to the vicinity of the transmitter of the handset. The receiver works in the GPS L-1 band at 1575.42MHz, which carries the C/A code.Recently, there has been an increased level of interest in GPS receivers [1][2][3]. A very low-power CMOS implementation, that uses a 2b quantizer and external loop-filters for its synthesizer and AGC, is reported in [2]. The receiver discussed in [4] uses a SAW filter for the IF filtering and an external loop-filter for the synthesizer.This chip uses an IF of 4.092MHz. Direct conversion and low-IF are the most popular wireless receiver architectures today. Direct conversion avoids the problem of image frequency, but issues associated with low-frequency noise, DC offset and LO-leakage make its implementation extremely difficult. Frequency planning of the proposed receiver is chosen to keep the reference clock harmonics and any wireless transmissions far away from the signal and image bands. Hence the primary requirement on image rejection is to reject the thermal noise in the image-band, and a relatively low image-rejection of 15dB can preserve the in-band SNR. A pre-select filter is required to keep the out-of-band signals from blocking the receiver. The block diagram of the receiver is shown in Fig. 17.1.1. The receiver uses no off-chip component, other than a crystal for reference clock and supply-decoupling capacitors. Except for the LNA, the entire receiver uses differential signal processing to improve immunity to supply and substrate disturbances.The LNA has single-ended input and differential output. Pinout is selected to isolate the RF signals from other package coupling. LNA uses tuned load designed with spiral inductors for improved linearity and NF. The LNA output is applied to two double-balanced mixers through capacitors used for AC coupling and matching. These two mixers perform down-conversion using I and Q components of LO. Subsequently, the IF-chain performs filtering and further amplification. The linearity of GPS signal in the presence of cellular-band jammers is one of the key performance parameters of this front-end.The first block in the IF-chain is a second-order regulated cascode stage. This filter rejects the out-of-band jammers, that are at least 140MHz away from GPS band. This block also provides lownoise amplification of the IF signal. The amplification in this stage comes from ratio of resistors and hence the required IQ balance ...

Texas Instruments, Dallas, TXWireless communication applications demand A/D converters with wide signal bandwidths up to 4 MHz and 12b to 14b or better resolution. Compared to switched-capacitor (SC) implementations, continuous-time (CT) ∆Σ modulators have the advantages of lower power consumption for wideband operation, intrinsic anti-alias filtering, and better immunity to the high leakage problems inherent to deep submicron technologies. Prior CT ∆Σ modulators have relied on one amplifier per pole to realize higher-order noise shaping [1,3]. This can lead to a long design process, complex layout, and increased power and area. In addition, amplifiers can be difficult to scale from one CMOS process node to another.To reduce design complexity and area, several solutions have been tried in the past. One of these solutions realizes a 2 nd -order passive ∆Σ modulator with a 2-pole passive filter and a 1b quantizer [2]. In the present work, a high-DR, fourth-order, single-bit, CT, ∆Σ modulator is achieved by adding an active 2 nd -order loop on top of the PDSM loop described in [2]. A 4 th -order loop is implemented using just two-amplifiers plus passive components to realize the poles and zeros. This active-passive combination (APDSM) runs at a sampling rate of 256MHz with a peak SNR of 86dB for a 600kHz signal bandwidth.The implemented APDSM architecture, using one amplifier per loop, is shown in Fig. 27.3.1. The outer loop has 2-poles and 1zero, and the inner loop has 2-poles and 2-zeros realized with passive elements. The double loop is designed to minimize internal signal swings. The input to the 1 st amplifier (AMP1) is limited to ±15mV peak and its output is limited to less than ±100mV peak. The inputs to the 2 nd amplifier (AMP2) and to the comparator are limited to ±5mV peak. These small-signal swings reduce distortion and power consumption, simplify amplifier design, and allow low voltage (1.2V) operation.AMP1, which provides most of the loop gain, is realized by a lowvoltage, folded-cascode OTA as shown in Fig. 27.3.2. This amplifier has a large differential input pair with non-minimum channel lengths (for reduced offset and flicker noise); hence it also has a large transconductance gain that helps reduce the inputreferred noise. Any noise coupled inside the inner loop is reduced by the transconductance-resistance G m -R gain of AMP1. AMP2, shown in Fig. 27.3.3, serves to decouple the poles and zeros of the inner and outer loops. Thus, passive RC values can be easily determined from loop-gain, bandwidth, signal swing, and absolute A/D gain requirements. AMP2 is implemented using a simple differential pair with non-cascoded loads. The G m -R gain of AMP2 helps to further suppress the input-referred noise and offset of the comparator. The cascaded G m -R gain in the forward path allows the comparator to be implemented as a very small, high-speed, regenerative latch comparator without offset cancellation as in Fig. 27.3.4.The loop filter passive poles and zeros are implemented using NWELL resistors and, PMOS ...

Highlights First time the solar-biogas-VRFB storage integrated IoT based smart microgrid is implemented. Optimized energy management has been demonstrated for the local community. Raspberry-Pi based low cost smart communication platform is used to monitor and control microgrid operation in real time. Available solar PV power is effectively utilized even during sudden grid outage at day time. 24 × 7 energy security is ensured by intelligent scheduling of RE sources and storage.

Use of Pulse Width Modulation (PWM) techniques has enabled the converters to be used in low-frequency high-power applications. The main objectives of PWM are to reduce the line current harmonic, switching energy loss, and torque pulsation and motor acoustic noise (for motor drive applications). This paper mainly deals with selective harmonic elimination PWM (SHEPWM), Hysteresis current controlled PWM (HCPWM), space vector PWM (SVPWM), bus-clamping PWM (BCPWM), and the most advanced wavelet PWM technique (WPWM). Different conventional as well as advanced soft computing