A 4/sup th/-order 86dB CT Δ/spl Sigmma/ ADC with two amplifiers in 90nm CMOS

Abstract

Texas Instruments, Dallas, TXWireless communication applications demand A/D converters with wide signal bandwidths up to 4 MHz and 12b to 14b or better resolution. Compared to switched-capacitor (SC) implementations, continuous-time (CT) ∆Σ modulators have the advantages of lower power consumption for wideband operation, intrinsic anti-alias filtering, and better immunity to the high leakage problems inherent to deep submicron technologies. Prior CT ∆Σ modulators have relied on one amplifier per pole to realize higher-order noise shaping [1,3]. This can lead to a long design process, complex layout, and increased power and area. In addition, amplifiers can be difficult to scale from one CMOS process node to another.To reduce design complexity and area, several solutions have been tried in the past. One of these solutions realizes a 2 nd -order passive ∆Σ modulator with a 2-pole passive filter and a 1b quantizer [2]. In the present work, a high-DR, fourth-order, single-bit, CT, ∆Σ modulator is achieved by adding an active 2 nd -order loop on top of the PDSM loop described in [2]. A 4 th -order loop is implemented using just two-amplifiers plus passive components to realize the poles and zeros. This active-passive combination (APDSM) runs at a sampling rate of 256MHz with a peak SNR of 86dB for a 600kHz signal bandwidth.The implemented APDSM architecture, using one amplifier per loop, is shown in Fig. 27.3.1. The outer loop has 2-poles and 1zero, and the inner loop has 2-poles and 2-zeros realized with passive elements. The double loop is designed to minimize internal signal swings. The input to the 1 st amplifier (AMP1) is limited to ±15mV peak and its output is limited to less than ±100mV peak. The inputs to the 2 nd amplifier (AMP2) and to the comparator are limited to ±5mV peak. These small-signal swings reduce distortion and power consumption, simplify amplifier design, and allow low voltage (1.2V) operation.AMP1, which provides most of the loop gain, is realized by a lowvoltage, folded-cascode OTA as shown in Fig. 27.3.2. This amplifier has a large differential input pair with non-minimum channel lengths (for reduced offset and flicker noise); hence it also has a large transconductance gain that helps reduce the inputreferred noise. Any noise coupled inside the inner loop is reduced by the transconductance-resistance G m -R gain of AMP1. AMP2, shown in Fig. 27.3.3, serves to decouple the poles and zeros of the inner and outer loops. Thus, passive RC values can be easily determined from loop-gain, bandwidth, signal swing, and absolute A/D gain requirements. AMP2 is implemented using a simple differential pair with non-cascoded loads. The G m -R gain of AMP2 helps to further suppress the input-referred noise and offset of the comparator. The cascaded G m -R gain in the forward path allows the comparator to be implemented as a very small, high-speed, regenerative latch comparator without offset cancellation as in Fig. 27.3.4.The loop filter passive poles and zeros are implemented using NWELL resistors and, PMOS ...

Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters

“…When considering FOMS, the hybrid second-order and fourth-order modulators present the FOM of 156.5 and 175, respectively, which demonstrate high power-efficiency among the modulators [2][3][4][5][6]. In particular, the fourth-order modulator in [7] employing a feedforward architecture presents an excellent energy-efficiency when both FOMW and FOMS are applied.…”

“…To alleviate the non-idealities of the comparator, several solutions have been tried in the past [5][6] where at least one active stage was used to suppress the inputreferred noise and the dc offset.…”

“…12a) from the inter-stage loading is to fully isolate the two passive stages from each other by using a buffer or an active integrator in the middle [5,6]. However, this is a power-consuming approach, which requires a power-hungry active integrator.…”

“…Delta-sigma modulator is a powerful ADC technique because of its higher accuracy in low-speed applications (e.g., medical applications). Passive integrator, as an alternative to the power-hungry active integrator, is a significant approach in the design of low-power and low-voltage delta-sigma (ΔΣ) modulators for reducing the analog power consumption [1][2][3][4][5][6]. However, due to the lack of DC gain inside the passive filter (or integrator), the modulator is sensitive to noise coupling, thereby affecting the signal-to-noise ratio (SNR).…”

“…The comparator non-idealities including noise, DC offset, and hysteresis directly limit the modulator resolution [5,6]. The third-order modulator in [5] makes use of the passive filter in the first and third stages and an active Gm-C filter in the middle stage in order to compensate for the loop gain and to mitigate the comparator's offset and noise.…”