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Single-electronic transistors (SETs) are considered as the attractive component for the next generation of transistors due to their ultrasmall size and low power consumption. Because SETs with single island cannot work at high temperature normally, more researchers begin to carry out research on the SETs with N-dimension multi-islands. In this paper, we introduce a new architecture of single-electron memory; ideally the memory should operate in combination of SETs with a nanowire of two-dimensional regular array of multiple tunnel junctions (MTJs). This structure is analyzed and studied with Monte Carlo simulator, SIMON. The Coulomb blockade effect and thermionic effect play an important role in carrier conduction in the system at room temperature. Nanowire MTJs are used as an electrometer to sense the memory-node charge. The well-defined parameter in tunnel junction circuits helps to obtain the charging of single electrons in these circuits at room temperature.

We propose a novel analytical model to describe the drain-source current as well as gate-source of single-electron transistors (SETs) at high temperature. Our model consists on summing the tunnel current and thermionic contribution. This model will be compared with another model

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