Design of a Single-Electron Memory Operating at Room Temperature

Abstract

Single-electronic transistors (SETs) are considered as the attractive component for the next generation of transistors due to their ultrasmall size and low power consumption. Because SETs with single island cannot work at high temperature normally, more researchers begin to carry out research on the SETs with N-dimension multi-islands. In this paper, we introduce a new architecture of single-electron memory; ideally the memory should operate in combination of SETs with a nanowire of two-dimensional regular array of multiple tunnel junctions (MTJs). This structure is analyzed and studied with Monte Carlo simulator, SIMON. The Coulomb blockade effect and thermionic effect play an important role in carrier conduction in the system at room temperature. Nanowire MTJs are used as an electrometer to sense the memory-node charge. The well-defined parameter in tunnel junction circuits helps to obtain the charging of single electrons in these circuits at room temperature.

Calculating the Coulomb blockade phase diagram in the strong coupling regime of a single-electron transistor: a quantum Monte Carlo study

“…where the sum ∑ k i ∈{k,ξ} stands for the accumulation of k j over the configurations ξ and k sampled by the Metropolis algorithm for the positive action in equation (11). The expectation value in equation ( 10) can proceed similarly.…”

“…By applying Green's non-equilibrium function approach [5][6][7], the CBPD for a lowconductance SET was calculated [4] and referred to as a weak coupling regime [8][9][10]. Utilizing the proposed method, one can determine the optimum temperature to operate a low-conductance SET for various applications, such as single-electron memory [11][12][13] and quantum dots [14], which trap and manipulate individual electrons, allowing researchers to explore quantum phenomena. Meanwhile, a high-conductance SET, i.e.…”

The Effect of Temperature on a Single-Electron Transistor I-V Curve

“…It is a fundamental device with ultra-low power consumption and high speed which can be used as random access memory. In addition, it also has the advantage of operating at room temperature [1]. The unique characteristic of SETs is the presence of an extremely small quantum dot in the channel.…”

Design and simulation of hybrid SET-CMOS inverter using macro-model technique

“…Indeed, a single charged impurity trapped in the insulating environment polarizes the island, creating on its surface an image charge of the order of e. This load is effectively subtracted from the external load [18]. Hybridization of SET with CMOS technology has emerged as a promising candidate for the next generation ultra-small [19][20][21], lowpower, high-speed Nano device. To understand the characteristics of SET-based circuits and explore its applications, simulation and modeling of this device has become of great importance [22][23][24][25].…”