The phase II upgrade of the HL-LHC experiments within the LHC intends to deepen the studies of the Higgs boson and to allow the discovery of further particles by adding an integrated luminosity of about 4000 fb -1 over 10 years of operation. This upgrade would overwhelm the installed pixel detector readout chips with higher hit rates and radiation levels than ever before. To match these extreme requirements the RD53 collaboration, a joint effort between ATLAS and CMS, developed RD53A, a new generation pixel detector readout chip prototype manufactured in a 65 nm CMOS technology. It is half the size of the final pixel chips and designed to meet requirements in the face of 3 GHz/cm 2 hit rate after irradiation to 500 Mrad. The detector is able to use 50x50 µm 2 or 25x100 µm 2 pixels with high readout speed of up to 4 links per chip with 1.28 Gbit/s each. Shunt-LDO regulators integrated on the bottom of the chip provide the required voltages to the two power domains, analog and digital. These regulators enable serial powering of the pixel modules, which is the only feasible, radiation hard scheme to ensure acceptable power cable losses and to stay within the material budget for the future pixel detectors. An overview of the status and challenges of serial powering and the Shunt-LDO regulator development will be given.
This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration. The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper.
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme requirements, such as: 50x50 µm pixels, high rate (3 GHz/cm 2 ), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator designed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.
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