Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

An experimental model is used to analyze the effects of ventricular stretching and verapamil on the activation patterns during VF. Ten Langendorff-perfused rabbit hearts were used to record VF activity with an epicardial multiple electrode before, during, and after stretching with an intraventricular balloon, under both control conditions and during verapamil (Vp) infusion (0.4-0.8 mumol). The analyzed parameters were dominant frequency (FrD) spectral analysis, the median (MN) of the VF intervals, and the type of activation maps during VF (I = one wavelet without block lines, II = two simultaneous wavelets with block lines, III = three or more wavelets with block lines). Stretch accelerates VF (FrD: 22.8 +/- 6.4 vs 15.2 +/- 1.0 Hz, P < 0.01; MN: 48 +/- 13 vs 68 +/- 6 ms, P < 0.01). On fitting the FrD time changes to an exponential model after applying and suppressing stretch, the time constants (stretch: 101.2 +/- 19.6 s; stretch suppression: 97.8 +/- 33.2 s) do not differ significantly. Stretching induces a significant variation in the complexity of the VF activation maps with type III increments and type I and II decrements (control: I = 17.5%, II = 50.5%, III = 32%; stretch: I = 7%, II = 36.5%, III = 56.5%, P < 0.001). Vp accelerates VF (FrD: 20.9 +/- 1.9 Hz, P < 0.001 vs control; MN: 50 +/- 5 ms, P < 0.001 vs control) and diminishes activation maps complexity (I = 25.5%, II = 60.5%, III = 14%, P < 0.001 vs control). On applying stretch during Vp perfusion, the fibrillatory process is not accelerated to any greater degree. However, type I and II map decrements and type III increments are recorded, though reaching percentages similar to control (I = 16.5%, II = 53%, III = 30.5%, NS vs control). The following conclusions were found: (1) myocardial stretching accelerates VF and increases the complexity of the VF activation pattern; (2) time changes in the FrD of VF during and upon suppressing stretch fit an exponential model with similar time constants; and (3) although stretching and verapamil accelerate the VF process, they exert opposite effects upon the complexity of the fibrillatory pattern.

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

A submerged anaerobic membrane bioreactor (AnMBR) demonstration plant with two commercial hollow-fibre ultrafiltration systems (PURON ® , KochMembrane Systems, PUR-PSH31) was designed and operated for urban wastewater treatment. An instrumentation, control, and automation (ICA) system was designed and implemented for proper process performance. Several singleinput-single-output (SISO) feedback control loops based on conventional on-off and PID algorithms were implemented to control the following operating variables: flow-rates (influent, permeate, sludge recycling and wasting, and recycled biogas through both reactor and membrane tanks), sludge wasting volume, temperature, transmembrane pressure, and gas sparging. The proposed ICA for AnMBRs for urban wastewater treatment enables the optimisation of this new technology to be achieved with a high level of process robustness towards disturbances.

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