On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Abstract

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

Neuropod: A real-time neuromorphic spiking CPG applied to robotics

“…An FPGA-based board was used to implement a digital system design, which controls the neuromorphic robot platform. This approach was considered in other similar works to implement a hardware version of CPGs, such as [8] and [19], and also in the field of neurorobotics and neuromorphic engineering [22]. This reconfigurable hardware offers flexibility against analog designs and adaptability in real time, in case of system failures.…”

Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity

“…It can scale from the 10k neurons in a worm brain up to 86B neurons in a human brain while using the same basic building blocks and architecture. This level of scalability is achieved via asynchronous distributed processing and event-based communication [10]. Inspired from biology, event-based simulation techniques were used for simulations of spiking neuron networks for a long time [11] and hardware implementation of asynchronous communication and processing is implemented in many of the available neuromorphic processors [12] [13] [14] [15] [16].…”

“…PilotNet is a neural network introduced by NVIDIA [42] along with the dataset 9 . The dataset contains video recording (10 frames per second) by a camera placed in front of the car as well as the corresponding steering angels for each frame of the video 10 . To find out the amount of redundancy (especially temporal sparsity) in this dataset, we compressed the raw frames using "Motion JPEG 2000 lossless compression" algorithm which resulted in 18 times reduction in size.…”

Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator

“…A baseboard, called DockSoC, designed for this MMP platform (manufactured by COBER) is able to manage all MMP needed power supplies (from 1V to 12V), the JTAG port over UART and several parallel interfaces to Neuromorphic chips over the CAVIAR and ROME parallel AER connectors are included [13]. The DockSoC can act as a daughter board for the AERNode [14] platform to expand connectivity to other PSoC platforms andor to support the connectivity to other Neuromorphic systems. Figure 2 shows a picture of the used setup with the PSoC platform, the DockSoC baseboard and a USB neuromorphic retina, called DAVIS.…”