An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Iakymchuk, Taras; Rosado, A.; Serrano-Gotarredona, Teresa; Linares-Barranco, B.; Jiménez-Fernández, Ángel; Linares-Barranco, A.; Jiménez-Moreno, Gabriel

doi:10.1109/iscas.2014.6865445

Cited by 29 publications

(34 citation statements)

References 12 publications

(8 reference statements)

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“…The experimental setup used to characterize both the isolated convolutional node and the whole network is shown in Figure 11 . An AER data player board (Serrano-Gotarredona et al, 2009 ) receives a list of AER events through a USB port and sends the events out to the AER-node board (Iakymchuk et al, 2014 ), where a Spartan6 FPGA is used to implement the different processing systems. The AER-node board sends out events to another board which communicates with a PC through a USB port (Serrano-Gotarredona et al, 2009 ).…”

Section: Resultsmentioning

confidence: 99%

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation

et al. 2018

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Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, following a specific organization of the connectivity pattern between layers of neurons known as receptive field. These networks have been traditionally implemented in software, but they are becoming more computationally expensive as they scale up, having limitations for real-time processing of high-speed stimuli. On the other hand, hardware implementations show difficulties to be used for different applications, due to their reduced flexibility. In this paper, we propose a fully configurable event-driven convolutional node with rate saturation mechanism that can be used to implement arbitrary ConvNets on FPGAs. This node includes a convolutional processing unit and a routing element which allows to build large 2D arrays where any multilayer structure can be implemented. The rate saturation mechanism emulates the refractory behavior in biological neurons, guaranteeing a minimum separation in time between consecutive events. A 4-layer ConvNet with 22 convolutional nodes trained for poker card symbol recognition has been implemented in a Spartan6 FPGA. This network has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1 s time. Different slow-down factors were applied to characterize the behavior of the system for high speed processing. For slow stimulus play-back, a 96% recognition rate is obtained with a power consumption of 0.85 mW. At maximum play-back speed, a traffic control mechanism downsamples the input stimulus, obtaining a recognition rate above 63% when less than 20% of the input events are processed, demonstrating the robustness of the network.

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Section: Resultsmentioning

confidence: 99%

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation

et al. 2018

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“… Hardware setup for demonstration of on-line real-time Stochastic Binary-Weights STDP learning. This setup contains an Event-Player (USBAER board) (Serrano-Gotarredona et al, 2009 ) to play back recorded AER events with precise timing, an AER-NODE board (Iakymchuk et al, 2014 ) which contains the Spartan-6 (XC6SLX150T-3) FPGA and a computer interfacing board (USBAERmini2) (Serrano-Gotarredona et al, 2009 ) to send the output AER events along with their time-stamps to a computer through USB. The computer uses jAER (Delbruck, 2007 ) to visualize and/or record events in real time displaying them as sequences of frames on a monitor screen.…”

Section: Methodsmentioning

confidence: 99%

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

et al. 2018

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In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

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“…Instead of the measures 58.56 Mevent/s of our prototype, in order to compare with the raw speed considered in other works, if only the transmission phase is considered, the maximum transmission speed is around 117 Mevent/s, same order of magnitude of other previous works [10,11,12]; however it is still far from the bandwidth obtained in the FACETS multilayer wafer scale neuromorphic system [18,6].…”

Section: Implementation Experimental Results and Discussionmentioning

confidence: 97%

“…Serial AER utilizes fewer wires, exhibits better performance and does not limit the data word-width. Several serial AER systems have been reported in literature demonstrating better performance than traditional parallel bus [10,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

et al. 2016

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Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.

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An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Cited by 29 publications

References 12 publications

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

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