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We demonstrate a 0.08 pm CMOS suitable for highperformance (vdd=1.8 V) and low-power applications (vdd < 1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for Leff down to 0.06 pm in the NFET and 0.08 pm in the PFET. Aggressive lateral and vertical dopant engineering allow the V, to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at Vd,=l V over the regular-VT process. INTRODUCTION AND DESIGN CRITERIADevice channel lengths are continually scaled to improve circuit performance and packing density. In addition to performance, the emergence of battery-powered applications have emphasized the need for good low-voltage operation. The primary goal for a high-performance sub-0.1 pm device design is to achieve the highest current drive for a given amount of short-channel effect or off-current. At reduced supply voltages, the threshold voltage must also be scaled to maintain adequate performance [l]. To maximize the functionality of a technology, the device design should be suitable for both high-performance and low-power applications with minor modifications. A major challenge is to maintain good short-channel effects in the low-v, case. To achieve these design goals, the following features are used: 1) super-steep retrograde channel; 2) different V,' s for highperformance and low-voltage applications by altering the channel dose; 3) 3.5 nm N 2 0 gate dielectric to improve performance and prevent boron penetration in the PFET; and (4) aggressive lateral dopant engineering to achieve good short-channel effects even at low V,'S.

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