A high-performance 0.08 μm CMOS

Abstract

We demonstrate a 0.08 pm CMOS suitable for highperformance (vdd=1.8 V) and low-power applications (vdd < 1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for Leff down to 0.06 pm in the NFET and 0.08 pm in the PFET. Aggressive lateral and vertical dopant engineering allow the V, to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at Vd,=l V over the regular-VT process. INTRODUCTION AND DESIGN CRITERIADevice channel lengths are continually scaled to improve circuit performance and packing density. In addition to performance, the emergence of battery-powered applications have emphasized the need for good low-voltage operation. The primary goal for a high-performance sub-0.1 pm device design is to achieve the highest current drive for a given amount of short-channel effect or off-current. At reduced supply voltages, the threshold voltage must also be scaled to maintain adequate performance [l]. To maximize the functionality of a technology, the device design should be suitable for both high-performance and low-power applications with minor modifications. A major challenge is to maintain good short-channel effects in the low-v, case. To achieve these design goals, the following features are used: 1) super-steep retrograde channel; 2) different V,' s for highperformance and low-voltage applications by altering the channel dose; 3) 3.5 nm N 2 0 gate dielectric to improve performance and prevent boron penetration in the PFET; and (4) aggressive lateral dopant engineering to achieve good short-channel effects even at low V,'S.

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

“…We present NMOS HC lifetime data over the stress drain voltage range V 2.9 V and the full range from below to above that show disagreement with the LEM. Moreover, these data are consistent with our proposed effective electron temperatures [9], [10] that for HC degradation in short NMOS devices, the worst case is not near the peak substrate current point (as predicted by the LEM), but at high .…”

“…The NFET devices used in this evaluation were built using the 0.08-m CMOS technology described by Su et al [10]. The devices have a 3.5-nm gate oxide thermally grown in N O, and contain shallow source/drain extension junctions and a counter-doped halo to suppress short channel effects.…”

Device scaling limits of Si MOSFETs and their application dependencies

“…On the other hand, the use of dynamic logic places an upper bound on individual FET leakage, creating a floor on values and forcing the use of somewhat larger thresholds than would be allowed by power considerations alone. Use of multiple threshold values [95] can moderate this constraint, but does not entirely remove the problem. A high degree of reliability is usually required by systems employing such technologies and often demands special screening and/or burn-in procedures.…”

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

“…For example see [1]- [8]. However, we have recently observed contrary results in an advanced logic technology [9]. Experimental data of 1.12 for the ratio of PFET to NFET (RATIO ), and 0.25 for the ratio of PFET to NFET (RATIO ) were obtained with identical polysilicon gate lengths for the NFET and PFET.…”