A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

Young, Ralph W.; Su, L.T.; Ieong, M.; Kapur, Sharad

doi:10.1109/55.701427

Cited by 7 publications

(1 citation statement)

References 13 publications

(8 reference statements)

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“…The dependence of the overlap capacitance on is stronger in pMOSFETs than in nMOSFETs due to the interfacial diffusion of boron underneath the gate edge. Similar results have been reported by Young et al [13] who considered that boron is easy to diffuse along the interface into the channel region.…”

Section: B Gate-extension Overlap Effectsupporting

confidence: 90%

A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling

Uchino

Ashburn

Kiyota

et al. 2004

IEEE Trans. Electron Devices

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Abstract-An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 sq has been realized. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1 m channel length and 40% higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25 nm enables excellent dc and high-speed circuit performance in 0.1-m devices.

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Section: B Gate-extension Overlap Effectsupporting

confidence: 90%