ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory

Titos-Gil, Ruben; Negi, Anurag; Acacio, Manuel E.; Garcia, Jose M.; Stenström, Per

doi:10.1109/tpds.2013.262

Cited by 14 publications

(14 citation statements)

References 21 publications

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“…[8], [27], [28] provides hardware support for a hybrid-mode execution of transactions. While the hybrid approach could boost performance, the complexity of implementing an unbounded lazy mode can be considerably high.…”

Section: Related Workmentioning

confidence: 99%

Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory

Zhao¹,

Chen

Draper³

2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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Hardware Transactional Memory (HTM) usually piggybacks onto the cache coherence protocol to detect data access conflicts between transactions. We identify an intrinsic mismatch between the typical coherence scheme and transaction execution, which causes a sizable amount of unnecessary transaction aborts. This pathological behavior is called false aborting and increases the amount of wasted computation and on-chip communication. For the TM applications we studied, 41% of the transactional write requests incur false aborting. To combat false aborting, we propose Predictive Unicast and Notification (PUNO), a novel hardware mechanism to 1) replace the inefficient coherence multicast with a unicast scheme to prevent transactions from being disrupted unnecessarily and 2) restrain transaction polling through proactive notification. PUNO reduces transaction aborts by 61% and network traffic by 32% in workloads representative of future TM applications with a VLSI implementation area overhead of 0.41%.

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Section: Related Workmentioning

confidence: 99%

Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory

Zhao¹,

Chen

Draper³

2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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“…It is argued in [4] that applying different policies at the granularity of cache lines could be more efficient. ZEBRA and SEL-TM are two new HTM designs that apply lazy and eager version management/conflict detection policies at the granularity of cache lines and mix the policies in transactions [4], [5]. However, both works don't discuss the correctness of their novel policies in detail.…”

Section: Related Workmentioning

confidence: 99%

“…As known to the author, two HTM designs have been proposed recently to apply complementary version management and conflict detection policies at the granularity of cachelinesize data instead of transaction to provide an additional dimension of flexibility [4], [5]. While the implementation and evaluation of both designs are nicely presented, the correctness issue of mixing lazy and eager version management in a HTM system is only briefly discussed.…”

Section: Introductionmentioning

confidence: 99%

On the Correctness of Mixing Lazy and Eager Version Management in Transactions

Zhao

Draper

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Transactional memory has been proposed as an optimistic concurrency-control construct to ease parallel programming. Hardware transactional memory (HTM) approaches implement version management and conflict detection in hardware to guarantee the correctness of transaction execution. Based on the style of version management and conflict detection, stateof-the-art HTM systems fall into two main types, namely lazy systems and eager systems. Neither system type is able to always perform better than the other over a wide range of applications due to the broad variations in the execution behaviors in typical parallel workloads.In this paper, we focus on the correctness of mixing lazy and eager version management in a log-based HTM. This hybrid type of version management is demonstrated to satisfy the requirement of atomicity and conflict serializability, which are critical for correctness. Furthermore, it is shown that the new approach does not violate the memory coherence formal model.

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“…The research community has explored this design space in depth, and a variety of proposed systems take advantage of transaction characteristics to simplify implementation and improve performance [2]- [5]. Hardware support for transactional memory has been implemented in Rock [6] from Sun Microsystems, Vega from Azul Systems [7], and Blue Gene/Q [8] and System z [9] from IBM.…”

Section: Introductionmentioning

confidence: 99%

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell

Goel

Titos-Gil

Negi

et al. 2014

2014 IEEE 28th International Parallel and Distributed Processing Symposium

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Hardware transactional memory implementations are becoming increasingly available. For instance, the Intel Core TM i7 4770 implements Restricted Transactional Memory (RTM) support for Intel Transactional Synchronization Extensions (TSX). In this paper, we present a detailed evaluation of RTM performance and energy expenditure. We compare RTM behavior to that of the TinySTM software transactional memory system, first by running microbenchmarks, and then by running the STAMP benchmark suite. We find that which system performs better depends heavily on the workload characteristics. We then conduct a case study of two STAMP applications to assess the impact of programming style on RTM performance and to investigate what kinds of software optimizations can help overcome RTM's hardware limitations.

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ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory

Cited by 14 publications

References 21 publications

Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory

Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory

On the Correctness of Mixing Lazy and Eager Version Management in Transactions

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell

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