Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell

Goel, Bhavishya; Titos-Gil, Ruben; Negi, Anurag; McKee, Sally A.; Stenström, Per

doi:10.1109/ipdps.2014.70

Cited by 34 publications

(13 citation statements)

References 19 publications

(19 reference statements)

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“…Mainly two reasons make long transactions better suited to run in SW rather than HW. First, transactions that persistently fail because of capacity issues will never be able to complete in HW as HTMs typically have limited transactional capacity [27]. Second, because the conflict detection granularity in STMs is usually finer than in HTMs, and all accesses inside a transaction are tracked to detect conflicts in most HTMs, hardware transactions are more susceptible to false conflicts than software transactions.…”

Section: Phtm*-an Efficient Phased Tm Algorithmmentioning

confidence: 99%

The Case for Phase-Based Transactional Memory

Carvalho

Araújo

Baldassin

2019

IEEE Trans. Parallel Distrib. Syst.

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In recent years, Hybrid TM (HyTM) has been proposed as a transactional memory approach that leverages on the advantages of both hardware (HTM) and software (STM) execution modes. HyTM assumes that concurrent transactions can have very different phases and thus should run under different execution modes. Although HyTM has shown to improve performance, the overall solution can be complicated to manage, both in terms of correctness and performance. On the other hand, Phased Transactional Memory (PhTM) considers that concurrent transactions have similar phases, and thus all transactions could run under the same mode. As a result, PhTM does not require coordination between transactions on distinct modes making its implementation simpler and more flexible. In this article we make the case for phase-based transactional systems using PhTM*, the first implementation of PhTM on modern HTM-ready processors. PhTM* novelty relies on avoiding unnecessary transitions to software mode by: (i) taking into account the categories of hardware aborts; (ii) adding a new serialization mode. Experimental results using Broadwell's TSX reveal that, for the STAMP benchmark suite, PhTM* performs on average 1.68x better than PhTM, a previous phase-based TM, 2.08x better than HyTM-NOrec, a state-of-the-art HyTM, and 2.28x better than HyCO, the most recent hybrid system in the literature. In addition, PhTM* also showed to be effective when running on a Power8 machine by performing over 1.18x, 1.36x and 1.81x better than PhTM, HyTM-NOrec and HyCO, respectively. We also show that STAMP applications do not exhibit hybrid behavior to justify the use of conventional hybrid systems, thus making PhTM* a better solution to those type of programs. Finally, we show for the first time that conventional hybrid systems do not perform better than phased-based system in a scenario with hybrid-behaved transactions.

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Section: Phtm*-an Efficient Phased Tm Algorithmmentioning

confidence: 99%

The Case for Phase-Based Transactional Memory

Carvalho

Araújo

Baldassin

2019

IEEE Trans. Parallel Distrib. Syst.

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“…HTM has been historically bad on SMT execution [9,12,30], mostly due to sharing scarce hardware resources between SMT threads. Since a transaction's footprint in SI-HTM is limited only by its write-set, we expect that, in some workloads, multiple SMT transactions on the same core will finally fit in a shared TMCAM.…”

Section: Hash-map Benchmarkmentioning

confidence: 99%

“…At a first glance, the recent emergence of hardware transactional memory (HTM) support in commercially available processors such as Intel Core and IBM POWER might seem like a perfect match to push the current generation of IMDBs to new performance levels. However, the limited capacity of HTM implementations [9,12,30] is incompatible with many real-world OLTP/OLAP workloads, whose access footprints are often much larger than the reduced capacity of existing HTM implementations [21].…”

Section: Introductionmentioning

confidence: 99%

Stretching the capacity of hardware transactional memory in IBM POWER architectures

Filipe

Issa

Romano

et al. 2019

Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming

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The hardware transactional memory (HTM) implementations in commercially available processors are significantly hindered by their tight capacity constraints. In practice, this renders current HTMs unsuitable to many real-world workloads of in-memory databases.This paper proposes SI-HTM, which stretches the capacity bounds of the underlying HTM, thus opening HTM to a much broader class of applications. SI-HTM leverages the HTM implementation of the IBM POWER architecture with a software layer to offer a single-version implementation of Snapshot Isolation. When compared to HTM-and softwarebased concurrency control alternatives, SI-HTM exhibits improved scalability, achieving speedups of up to 300% relatively to HTM on in-memory database benchmarks.

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“…Outros trabalhos [de Carvalho et al 2013, Diegues et al 2014, Goel et al 2014 também analisam o impacto no consumo de energia do pacote STAMP usando o Haswell TM . Em particular, o trabalho de Goel et al [Goel et al 2014] realiza uma caracterização que explora os limites do hardware para características como tamanhoś otimos para transações e taxa de contenção.…”

Section: Trabalhos Relacionadosunclassified

Reavaliando o Conjunto de Aplicações STAMP em um Novo Hardware Transacional

Carvalho¹,

Murari²,

Baldassin³

2015

Anais Do XVI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2015)

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Nos últimos quatro anos, IBM® e Intel® disponibilizaram processadores com suporte para memória transacional. A maioria dos trabalhos avaliaram esses processadores usando as aplicações STAMP e consideraram apenas as causas de cancelamentos das aplicações como um todo. Neste trabalho, apresenta-se uma análise por transação do STAMP e contrasta-se diferentes métricas de desempenho para determinar os motivos fundamentais pelo baixo desempenho do HaswellTM em algumas aplicações. Em resumo, os resultados mostram que uma transação domina o tempo de execução e tem poucas efetivações porque excede a capacidade restrita do processador, ou gera muitos conﬂitos quando executada em hardware.

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Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell

Cited by 34 publications

References 19 publications

The Case for Phase-Based Transactional Memory

The Case for Phase-Based Transactional Memory

Stretching the capacity of hardware transactional memory in IBM POWER architectures

Reavaliando o Conjunto de Aplicações STAMP em um Novo Hardware Transacional

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