Reavaliando o Conjunto de Aplicações STAMP em um Novo Hardware Transacional

Carvalho, João Pedro; Murari, Rafael; Baldassin, Alexandro

doi:10.5753/wscad.2015.14285

Cited by 2 publications

(5 citation statements)

References 30 publications

(27 reference statements)

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“…As a result, a phase-based TM system is better suited than a hybrid alternative because there is no point in time in which any two transactions will diverge on the best performing execution mode. The SPMD nature of STAMP applications combined with the fact that a single transaction dominates execution time [55] also supports our claim. Figure 5.6 also shows how effective PhTM* is to both detect and remain on the best mode.…”

Section: Behavior Of Stamp Applicationssupporting

confidence: 83%

“…Apart from these applications, only Yada and Intruder might have space for improvement as Figure 6.1 shows. As previous results show [55], both Kmeans and SSCA2 exhibit very small speedups in SW and are more fitted to HTM. The version of Labyrinth modified by Spear et al [91] has very short transactions, with very low conflict probability and, therefore exhibits only a negligible overhead with libitm compared to manual instrumentation.…”

Section: Pragma Elidebar To the Rescuesupporting

confidence: 69%

“…Finally, the whole sequence is reconstructed with the points that were found. The first step alone takes over 90% of Genome execution time [55] and the only data structure modified by multiple threads is the hash-table. Nevertheless, GCC inserts barriers on all functions used to compare nucleotide segments, even though segments are read-only at this step.…”

Section: Transactional Memory Support On Gccmentioning

confidence: 99%

“…Each step has a thread-wait barrier at the end, so threads only move to the next step once all of them have finished the previous one. The first step takes over 90% of the Genome execution time [55] and in that step the only data which is modified by multiple threads is the hash-table itself. Thus, the only required barriers are those accessing the hasthtable.…”

Section: Breakdown Of Stamp Transactional Accessesmentioning

confidence: 99%

“…This is usually the case when a new application is being coded for the first time, but might require a lot of time otherwise. In the case of the STAMP benchmarks, we reported the results for the two applications (Genome and Vacation) we had chosen (based on the profile stage of Subsection 6.5.2 and previous work [55]). Apart from these applications, only Yada and Intruder might have space for improvement as Figure 6.1 shows.…”

Section: Pragma Elidebar To the Rescuementioning

confidence: 99%

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Improving hardware/software transactional memory codesign

Carvalho¹

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The time when computers were considered just another luxury commodity to have at home or an expensive tool to crunch numbers are long gone. Nowadays, computer science and engineering are at the core of recent advances in many research fields. However, the ever-increasing demand for performance still imposes a challenge to both computer scientists and industry. For decades, the microprocessor industry successfully provided a steady performance increase with each new processor release, leveraged by Moore's Law continuous improvement of semiconductor technology. As power density boundaries in semiconductor technology have been reached, the shift from single-core to multicore processing has become the most relevant performance improvement tool in modern computer design. Despite the great potential of multicore machines to meet today's demands, their adoption is still modest mainly due to the challenging aspect of concurrent programming. Most concurrent programming models available require programmers to explicitly write their code in a way that all cores are used. Yet the task of synchronizing multiple concurrent accesses to shared resources has proven to be error-prone and far from trivial. In this direction, the Transactional Memory (TM) programming model provides a simple and transparent abstraction to express what needs to be synchronized, without requiring the programmer to write synchronization code. TM has the potential to greatly simplify the exploitation of the parallelism available on multicore architectures while simplifying the programmers' task. Nonetheless, TM usage and adoption is mostly restricted to research applications, although a large body of research shows the benefits and great performance results that software, hardware and hybrid transactional systems enable. In fact, recently leading researchers in the area backed-off from presenting a revised technical specification for standardizing TM in C/C++, after many failed attempts, mainly due to the lack of usage experience. Moreover, although conventional hybrid TM systems allow different transactions to operate in hardware and software, simultaneously, such systems were proven to be inherently limited. Phase-based transactional systems (PhasedTM) are another class of hybrid TMs that execute transactions in non-overlaped phases but, prior to the work described in this manuscript, they were considered as an inferior hybrid variant. In this direction, this thesis makes two contributions to the field of TM. First, it makes a solid case in favor of phase-based transactional memory. And second, it shows how extended compiler support for TM can be used to automatically generate high-performance transactional code. More specifically, this work builds a case for phase-based transactional systems, which were, so far, regarded as inferior variations of conventional hybrid transactional systems. In addition, it proposes a novel annotation mechanism (TMElide) to selectively eliminate unnecessary transactional memory barriers from compiler generated code. This...

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Section: Behavior Of Stamp Applicationssupporting

confidence: 83%

Section: Pragma Elidebar To the Rescuesupporting

confidence: 69%

Section: Transactional Memory Support On Gccmentioning

confidence: 99%

Section: Breakdown Of Stamp Transactional Accessesmentioning

confidence: 99%

Section: Pragma Elidebar To the Rescuementioning

confidence: 99%

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