Width minimization of two-dimensional CMOS cells using integer programming

Gupta, A.; Hayes, John P.

doi:10.1109/iccad.1996.571346

Cited by 15 publications

(17 citation statements)

References 13 publications

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“…Gupta and Hayes [3] [4] proposed the CMOS cell width minimization via Integer Linear Programming (ILP). This method solves the width minimization of two dimensional transistor placement exactly.…”

Section: Imentioning

confidence: 99%

“…The layouts generated by our method are equal to or smaller than the one dimensional layout generated by Gupta and Hayes' method [3] which treats complementary P-/NMOSFETs pair. For example the width of the full adder fad1 in Table II is 15 using our method whereas the minimum width of the one dimensional layout of the full adder described in [3] is 16.…”

Section: E Rmentioning

confidence: 99%

“…For example the width of the full adder fad1 in Table II is 15 using our method whereas the minimum width of the one dimensional layout of the full adder described in [3] is 16.…”

Section: E Rmentioning

confidence: 99%

See 2 more Smart Citations

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

Iizuka¹,

Ikeda²,

Asada³

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Section: Imentioning

confidence: 99%

Section: E Rmentioning

confidence: 99%

See 1 more Smart Citation

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

Iizuka¹,

Ikeda²,

Asada³

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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“…In the same manner as stated in [10], we summarize in Table I the assumptions underlying the 2-D array layout. Fig.…”

Section: B Layout Generationmentioning

confidence: 99%

“…An Integer Linear Programming(ILP) method is used in the automatic layout generation of CMOS cells [10], where the 2-D array height minimization problem for CMOS cells is dened as a covering problem { a subset of chains that covers each transistor and has the minimum cell height, needs to be determined. However, the set of all chains which are generated from an n-side graph is too large to be solved by ILP.…”

Section: B Layout Generationmentioning

confidence: 99%

Layout generation of array cell for NMOS 4-phase dynamic logic

Furuie

Song

Yoshida

et al.

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Abstract| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M2N)+2 transistors so as to constitute each t ype of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A n umber of experimental results demonstrate the practicability o f the proposed approach.

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Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells

Gupta¹,

Hayes²

Proceedings of the 34th Design Automation Conference

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We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2-0 ) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2 -0 layout of minimum width Wcelb Then, another model generates a 2 -0 layout that has width Wce[l and requires a minimum number of routing tracks. Run times are in seconds for circuits with up to 16 transistors. For larger circuits, we extend CLIP to a hierarchical method HCLIP that places series-connected transistors contiguously. This reduces run times by up to three orders of magnitude, and still yields optimal results in over 80% of cases.

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Width minimization of two-dimensional CMOS cells using integer programming

Cited by 15 publications

References 13 publications

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

Layout generation of array cell for NMOS 4-phase dynamic logic

Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells

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