Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells

Gupta, A.; Hayes, John P.

doi:10.1109/dac.1997.597190

Cited by 6 publications

(5 citation statements)

References 11 publications

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“…Tani et al [1991] and Gupta and Hayes [1997] discussed a style in which two-dimensional layouts are formed from multiple one-dimensional rows. The former presented a heuristic technique based on min-cut partitioning while the latter presented an exact formulation, called CLIP, based on integer linear programming.…”

Section: Prior Workmentioning

confidence: 99%

Transistor placement for noncomplementary digital VLSI cell synthesis

Riepe

Sakallah²

2003

ACM Trans. Des. Autom. Electron. Syst.

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There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized "functional cell" style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimization is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.

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Section: Prior Workmentioning

confidence: 99%

Transistor placement for noncomplementary digital VLSI cell synthesis

Riepe

Sakallah²

2003

ACM Trans. Des. Autom. Electron. Syst.

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“…Tani et al [117] and Gupta & Hayes [34,35,36] have both presented multiple-row 1-1/2 dimensional cell synthesis systems. The former discuss a heuristic technique based on min-cut partitioning while the latter developed an exact formulation, called CLIP, based on integer linear programming.…”

Section: One and One-half Dimensional Cell Synthesismentioning

confidence: 99%

“…ILPs are much more computationally intensive to solve. [115] and makes use of techniques from Devadas [21] and Gupta and Hayes [34,35]. As described in Section 2.4, each pair of objects can be in one of four possible relative positions, and this is enforced by introducing four constraints between every pair of objects , exactly one of which will be "active" in any given solution.…”

Section: Optimization Formulationsmentioning

confidence: 99%

Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

Riepe

Sakallah

1999

Proceedings of the 1999 International Symposium on Physical Design

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There is an increaing need in mo&m VLSI designs for circuits implemented in high-peqonnance logic families such as Cascade Voltage Switch Logic, Pass Transistor Logic, and domino CMOS. Circuits designed in these non-dual ratioed logic fmnilies can be highly irregular with complex geometry sharing and non-trivial muring. Tmditional digital cell layout synthesis tools derivedfrom the mw-based "+tional cell" style break down when confnmted with such circuit topologies. These cells require a full-custom 2-dimensional layout style which cum&y requires skilled manual design In this work we dejne the synthesis of complex 2-dimensional digital cells as a new problem which we call transistor-level micro-placement and routing. To address this problem we develop a complete end-to-end methodology which is implemented in a prototype tool named TEMPO. Our primary focus in this work is the micro-placement problem. We explore techniques for the modeling and dynamic optimization of geometry sharing though transistor chaining and arbitrary geometry merging. Experiments conducted with a new set of benchmark circuits show promising results when TEMPO is compared to a commercial cell synthesis tool.

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“…Gupta and Hayes [3] [4] proposed the CMOS cell width minimization via Integer Linear Programming (ILP). This method solves the width minimization of two dimensional transistor placement exactly.…”

Section: Imentioning

confidence: 99%

“…To conduct the experiment, we also transformed the transistor placement problems into the 0-1 ILP problems. Our formulation of the ILP is based on the Gupta and Hayes' formulation [4]. The differences are that we assume only one dimensional placement and P-/NMOSFETs with the same gate nodes can be aligned vertically, while they assumed two dimensional placement and only complementary P-/N-MOSFETs can be aligned vertically.…”

Section: E Rmentioning

confidence: 99%