High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

Iizuka, Tetsuya; Ikeda, Makoto; Asada, Kunihiro

doi:10.1109/aspdac.2004.1337556

Cited by 8 publications

(6 citation statements)

References 8 publications

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“…Being this aspect a constraint for some placement methodologies [8,9], a nonplanar cell can be a problem for an efficient automatic layout generation based on these methodologies, also increasing the routing procedure caused by the non-planar connection.…”

Section: Problem Descriptionmentioning

confidence: 99%

Topological characteristics of logic networks generated by a graph-based methodology

Cardoso

Zanandrea

Souza

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.

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Section: Problem Descriptionmentioning

confidence: 99%

Topological characteristics of logic networks generated by a graph-based methodology

Cardoso

Zanandrea

Souza

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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“…Our method utilizes the procedure proposed by [4] to generate the minimum width transistor placements. In [4], the minimum width placements are generated one by one until a routable placement is found via Boolean Satisfiability.…”

Section: Transistor Placementmentioning

confidence: 99%

“…In [4], the minimum width placements are generated one by one until a routable placement is found via Boolean Satisfiability. We apply this method and generate all possible minimum width placement comprehensively under our layout styles.…”

Section: Transistor Placementmentioning

confidence: 99%

See 2 more Smart Citations

Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells

Iizuka

Ikeda

Asada

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

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Library cell layout with Alt-PSM compliance and composability

Cao¹,

Dhawan²,

Hu³

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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The sustained miniaturization of VLSI feature size presents great challtmges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET). The difficulty and feasibility of deploying the RET such as Alternating Phase Shifting Mask (Alt-PSM) depend heavily on circuit layout. In this paper,. we propose a Boolean satisfiability (SAT) based library cell layout method that can achieve Alt-PSM compliance and composability in a constructive manner. Compared to previously reported post processing approach: our method often leads to further cell area efficiency improvement. 0-7803-8736-8/051$20.00 02005 IEEE.

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High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

Cited by 8 publications

References 8 publications

Topological characteristics of logic networks generated by a graph-based methodology

Topological characteristics of logic networks generated by a graph-based methodology

Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells

Library cell layout with Alt-PSM compliance and composability

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