Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells

Iizuka, Tetsuya; Ikeda, Makoto; Asada, Kunihiro

doi:10.1109/isqed.2004.1283703

Cited by 10 publications

(2 citation statements)

References 8 publications

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“…for open defects on a wire W i and the critical area A s ij (x) for short defects between two parallel wires W i and W j can be approximated as follows [7], [20], [22]:…”

Section: Critical Area and The Pofmentioning

confidence: 99%

Track Routing and Optimization for Yield

Cho

Xiang

Puri

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield optimization. However, a straightforward formulation of yield-driven track routing can be shown to be integer nonlinear programming, which is a nondeterministic polynomial-time complete problem. TROY overcomes the computational complexity by combining two effective techniques, i.e., the minimum Hamiltonian path (MHP) from graph theory and the second-order cone programming (SOCP) from mathematical optimization. First, TROY performs wire ordering to minimize the critical area for short defects by finding an MHP. Then, TROY carries out optimal wire sizing/spacing through SOCP optimization based on the given wire order. Since the SOCP can be optimally solved in near linear time, TROY efficiently achieves globally optimal wire sizing/spacing for the minimal POF.Index Terms-Minimum Hamiltonian path (MHP), physical design, random defects, second-order cone programming (SOCP), track routing, yield.

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“…for open defects on a wire W i and the critical area A s ij (x) for short defects between two parallel wires W i and W j can be approximated as follows [7], [20], [22]:…”

Section: Critical Area and The Pofmentioning

confidence: 99%

Track Routing and Optimization for Yield

Cho

Xiang

Puri

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…where x is the defect size, x min is the minimum resolvable lithographic feature size, k is a coefficient to ensure ∞ x min F (x) dx = 1, and r ≈ 3 [37]. When the end effect is ignored [38], the critical area A o i (x) for open defects on a wire W i and the critical area A s ij (x) for short defects between two parallel wires W i and W j can be approximated as follows [20,36,39]:…”

Section: Critical Area Aware Routing For Random Defect Minimizationmentioning

confidence: 99%