The sustained miniaturization of VLSI feature size presents great challtmges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET). The difficulty and feasibility of deploying the RET such as Alternating Phase Shifting Mask (Alt-PSM) depend heavily on circuit layout. In this paper,. we propose a Boolean satisfiability (SAT) based library cell layout method that can achieve Alt-PSM compliance and composability in a constructive manner. Compared to previously reported post processing approach: our method often leads to further cell area efficiency improvement. 0-7803-8736-8/051$20.00 02005 IEEE.
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