Transistor placement for noncomplementary digital VLSI cell synthesis

Abstract

There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized "functional cell" style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimization is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.

New perspectives in VLSI design automation: deterministic packing by Sequence Pair

“…This problem appears both, in the context of fully two-dimensional leaf-cells design methodology (Riepe and Sakallah 2003) (at the transistor level), as well as in the context of more general application, i.e., in the floorplanning step of nowadays, hierarchical VLSI design flows . The importance of this particular problem caused, that the intensive research effort has been made during past two decades.…”

cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells

“…XPRESS uses exact algorithms and heuristics to generate the minimum graph covering using transistor trails, minimizing diffusion gaps and overall width. CELLERITY, TEMPO [24], and ASTRAN [31] use a simulated annealing framework for placement. These works use cost functions that incorporate cell width, transistor ordering and orientation, gate alignment, and routing quality.…”

“…Alternatively, Gopalakrishnan [12] uses a greedy heuristic to do an intra-row refinement as the last phase of a multi-stage placement strategy. Using heuristic algorithms allows cell generators to explore beyond the traditional row-placement layout style, as in [24], and to some extent [12]. Heuristics, however, usually require a compaction stage to achieve designs comparable to hand-optimized layout.…”

Area-Optimal Transistor Folding for 1-D Gridded Cell Design

“…Finding the transistor arrangement with the best routability characteristics is the goal of algorithms for transistor placement (e.g., [1], [16]) and is out of the scope of this work.…”

“…The algorithms proposed to find these orderings are tightly related to the theory of finding Eulerian paths in undirected graphs. Several theoretical results and algorithms have been proposed to find optimal transistor orderings, either considering fixed transistor netlists [16], [20] or allowing transistor reordering of series-parallel graphs while preserving the functionality of the cells [13], [14].…”