Layout generation of array cell for NMOS 4-phase dynamic logic

Abstract

Abstract| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M2N)+2 transistors so as to constitute each t ype of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A n umber of experimental results demonstrate the practicability o f the proposed approach.