Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump

Kazeminia, Sarang; Mowloodi, Sobhan Sofi; Hadidi, Khayrollah

doi:10.1109/iraniancee.2014.6999518

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…In addition, using frequency synthesizers and multipliers based on DLLs has increased frequency range remarkably. A lot of DLL structures to increase frequency range has been developed . As an example, a DLL for a synchronous clocking is analyzed in Kim and Kim to increase operating range.…”

Section: Introductionmentioning

confidence: 99%

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A wide range delay locked loop for low power and low jitter applications

Estebsari

Gholami

Ghahramanpour

2017

Circuit Theory & Apps

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Summary In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.

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Section: Introductionmentioning

confidence: 99%

“…lot of DLL structures to increase frequency range has been developed. [4][5][6] As an example, a DLL for a synchronous clocking is analyzed in Kim and Kim 7 to increase operating range. This DLL uses lock detect circuit, multiplexer, 2 comparators, and 1 AND gate to have a wide frequency range.…”

mentioning

confidence: 99%