A wide range delay locked loop for low power and low jitter applications

Estebsari, Motahhareh; Gholami, Mohammad; Ghahramanpour, Mohammad Javad

doi:10.1002/cta.2401

Cited by 13 publications

(8 citation statements)

References 15 publications

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“…Initially, the output of the detectors is zero, and the comparator output is equal to 1 V. Thus, a big voltage is applied to the gate of the transistors M1 and M2 in the proposed VCO circuit. This big voltage produces a high current according to Equation (1). This current creates strong initialization conditions for the oscillator.…”

Section: Designing Mixermentioning

confidence: 99%

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Design of a 41.14–48.11 GHz Triple Frequency Based VCO

et al. 2019

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Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier.

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Section: Designing Mixermentioning

confidence: 99%

“…Recently, there has been an increased demand in radio frequency design [1][2][3]. One of the most important blocks in transceiver communication systems are the voltage controlled oscillators (VCOs) [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

et al. 2019

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“…However, the reference and the voltage control delay line (VCDL) secondary jitter have been ignored in these papers. There are great methods for improving jitter in Gholami et al, 15‐21 but they did not present a mathematical analysis. In this work, a delay error equation is presented that is more accurate than previous works.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a low jitter delay‐locked loop using lock state detector

Modanlou

Ardeshir

Gholami

2021

Circuit Theory & Apps

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Summary In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V.

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“…An analog PLL circuit according to Fig. 2 consists of important blocks of phase frequency detector (PFD), charge pump (CP), loop filter (LF) and voltage-controlled oscillator (VCO) [9], so one of the main difference between phase locked loop and delay locked loop (DLL) is that delay locked loop uses voltage controlled delay line instead of VCO [10][11]. In an analog PLL, a phase frequency detector, receives its inputs from reference input signal and the output of VCO and its output is based on phase difference between its inputs.…”

Section: Introductionmentioning

confidence: 99%

A Wide Range and High Swing Charge Pump for Phase Locked Loop in Phasor Measurement Unit

Estebsari

2019

2019 IEEE International Conference on Environment and Electrical Engineering and 2019 IEEE Industrial and Commercial Power Syst

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Phasor Measurement Units are widely utilized in power systems to provide synchrophasor data for a verity of applications, mainly performed by Energy Management Systems (EMS). Synchrophasors are measured at different parts of the network and transmitted to Phasor Data Concentrator (PDC) at a rate of 30-60 samples per second. The synchronization is done by means of a phase locked oscillator inside PMU which uses clock signal of the Global Positioning System (GPS). In this paper a novel charge pump with an appropriate operation capability in phaselocked-loops is presented. By using this phase locked loop in phase measurement unit, the total performance of this circuit will be improved. The proposed charge pump uses current mirror techniques in order to achieve a wide range of output voltage to control the oscillator and also has a good performance in a wide range of frequency from 33MHz to 555MHz. This circuit is designed and simulated in TSMC 0.18um CMOS technology. The proposed charge pump only consumes 390uW power in supply voltage of 1.8V at 500MHz and has a maximum current of 16.43uA with a acceptable current matching between source and sink currents. It is also capable to be used in a wide frequency range and low power applications.

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A wide range delay locked loop for low power and low jitter applications

Cited by 13 publications

References 15 publications

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Analysis and design of a low jitter delay‐locked loop using lock state detector

A Wide Range and High Swing Charge Pump for Phase Locked Loop in Phasor Measurement Unit

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