Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Nasri, A.; Toofan, Siroos; Estebsari, Motahhareh; Estebsari, Abouzar

doi:10.3390/electronics8050529

Cited by 3 publications

(1 citation statement)

References 23 publications

(31 reference statements)

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“…The source damping resistors and LC filter placed at the current source are also tried to achieve a good phase noise performance. In another attempt to facilitate the phase splitting using quadrature VCO topology in K Band (Nasri et al , 2019), efforts are made to combine the super-harmonic coupling using 2nd harmonic in a stand-alone free-running differential oscillator using frequency doubler. The approach promises a rather wider application at the cost of phase noise and linearity.…”

Section: Introductionmentioning

confidence: 99%

Low power LC-voltage controlled oscillator with −140 dBc/Hz @ 1 MHz offset using on-chip inductor design in 0.13 µm RF-CMOS process for S-Band application

Balodi

Verma²,

Paravastu

2019

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Purpose The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research. Design/methodology/approach This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO. Findings The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs. Research limitations/implications Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it. Practical implications The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications. Originality/value The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.

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Section: Introductionmentioning

confidence: 99%

Low power LC-voltage controlled oscillator with −140 dBc/Hz @ 1 MHz offset using on-chip inductor design in 0.13 µm RF-CMOS process for S-Band application

Balodi

Verma²,

Paravastu

2019

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Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 µm RF-CMOS Process for Modern WLAN Application

Khan

Balodi

Misra³

2022

Circuits Syst Signal Process

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A Wide Range and High Swing Charge Pump for Phase Locked Loop in Phasor Measurement Unit

Estebsari

2019

2019 IEEE International Conference on Environment and Electrical Engineering and 2019 IEEE Industrial and Commercial Power Syst

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Phasor Measurement Units are widely utilized in power systems to provide synchrophasor data for a verity of applications, mainly performed by Energy Management Systems (EMS). Synchrophasors are measured at different parts of the network and transmitted to Phasor Data Concentrator (PDC) at a rate of 30-60 samples per second. The synchronization is done by means of a phase locked oscillator inside PMU which uses clock signal of the Global Positioning System (GPS). In this paper a novel charge pump with an appropriate operation capability in phaselocked-loops is presented. By using this phase locked loop in phase measurement unit, the total performance of this circuit will be improved. The proposed charge pump uses current mirror techniques in order to achieve a wide range of output voltage to control the oscillator and also has a good performance in a wide range of frequency from 33MHz to 555MHz. This circuit is designed and simulated in TSMC 0.18um CMOS technology. The proposed charge pump only consumes 390uW power in supply voltage of 1.8V at 500MHz and has a maximum current of 16.43uA with a acceptable current matching between source and sink currents. It is also capable to be used in a wide frequency range and low power applications.

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Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Cited by 3 publications

References 23 publications

Low power LC-voltage controlled oscillator with −140 dBc/Hz @ 1 MHz offset using on-chip inductor design in 0.13 µm RF-CMOS process for S-Band application

Low power LC-voltage controlled oscillator with −140 dBc/Hz @ 1 MHz offset using on-chip inductor design in 0.13 µm RF-CMOS process for S-Band application

Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 µm RF-CMOS Process for Modern WLAN Application

A Wide Range and High Swing Charge Pump for Phase Locked Loop in Phasor Measurement Unit

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