Wide-division-range high-speed fully programmable frequency divider

Sleiman, S.B.; Atallah, Jad G.; Rodriguez, Saul; Rusu, Ana; Ismail, Mohammed

doi:10.1109/newcas.2008.4606310

Cited by 9 publications

(3 citation statements)

References 10 publications

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“…On the feedback path, a high-speed programmable divider is used to bring the carrier frequency down to a fixed frequency of 499.2 MHz. The divider incorporates the control logic into a conventional cascade prescaler and achieves an extended division ratio of 8-31 with four prescalers [12], [13]. The 499.2-MHz clock can be used as the chip rate clock, or fed to a frequency doubler to generate the 998.4-MHz clock for the receiver back-end [7].…”

Section: A Wideband Pll With Dual Lc Qvco Coresmentioning

confidence: 99%

A 5–10-GHz Highly Configurable IEEE 802.15.4a/4z-Compatible IR-UWB Coherent Transmitter in 28-nm CMOS

Zhang

Nguyen

Chen

et al. 2023

IEEE Microw. Wireless Tech. Lett.

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This letter presents an IEEE 802.15.4a/4z-compliant integrated impulse radio ultrawideband (IR-UWB) coherent transmitter that supports all channels in Band 2 from 6.5 to 10 GHz. A wideband phase-locked loop (PLL) with dual LC quadrature voltage-controlled oscillators (QVCOs) is implemented that covers more than 5-GHz frequency range. The PLL features a phase noise of −99.8 dBc/Hz at 1-MHz frequency offset and an rms jitter of 2.3 ps, which ensures reliable coherent operation. The quadrature clocks also make easy future I/ Q receiver integration. The pulse envelope and width are digitally controlled, thanks to our flexible digital pulseshaping configuration. Implemented in a 28-nm CMOS process with a supply voltage of 0.9 V, the chip occupies a core area of 0.21 mm 2 and supports channel 5-15 with a peak pulse repetition frequency (PRF) of 499.2 MHz. The transmitter has a maximum output swing of 430 mV and the power consumption is 1.3 nJ/pulse at a PRF of 15.6 MHz.

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Section: A Wideband Pll With Dual Lc Qvco Coresmentioning

confidence: 99%

A 5–10-GHz Highly Configurable IEEE 802.15.4a/4z-Compatible IR-UWB Coherent Transmitter in 28-nm CMOS

Zhang

Nguyen

Chen

et al. 2023

IEEE Microw. Wireless Tech. Lett.

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show abstract

“…In most of published works, current mode logic (CML) [2,3] or dynamic logic [4,[6][7][8][9][10][11][12][13][14][15][16] has been used in design of dividers. While CML based dividers can achieve high speed and even work with low-amplitude input signals; their static power dissipation limits use of them for power-conscious applications.…”

Section: Introductionmentioning

confidence: 99%

A novel topology for modular frequency dividers with enhanced speed and power efficiency

Farsiani

Sahafi

Sobhi

2015

Analog Integr Circ Sig Process

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In this paper, we introduce a new topology for modular frequency dividers which improves the speed and decreases the power consumption in true-single-phaseclock (TSPC) based dividers and enhances the speed in their Extended-TSPC (E-TSPC) based counterparts. Two dividers are designed in 0.18 lm TSMC CMOS technology with 1.8 V supply voltage, to examine the speed and power efficiency of proposed structure. Post-layout simulation results reveal that in TSPC based design, use of proposed structure leads to about 38 % power reduction compared to the conventional topology. In addition, the E-TSPC based design achieves the speed as high as static dividers with maintaining the programmability and modularity of divider.

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“…The divide-by-N frequency divider [1,7,28,30,46], also known as an integer-N divider, exploits a large wide-range division ratio which can vary from 2 to N where N is an arbitrary integer value less than 2 M for an M-bit divider. Even though the division ratio is not as flexible as a programmable swallow counter and the operation is not as fast as an asynchronous prescaler divider, research has shown that the integer-N frequency divider is more practical in terms of design time, continued cost-effective technology scaling, and has low spurious sideband effects compared to a fractional-N (i.e.…”

Section: Introductionmentioning

confidence: 99%

A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure

Abdel-Hafeez

Gordon‐Ross

2011

Circuits Syst Signal Process

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We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling effect. The pipeline latencies are precluded due to the use of a subtractor circuit that "swallows" any additional cycles. Furthermore, our frequency divider is easily scalable to large divider widths due to the use of modular component architecture. The fan-in and fan-out are independent of the divider width, thus making the structure attractive for regular VLSI implementation and continued technology scaling. We implemented our proposed divider using a 0.15-µm TSMC digital cell library and achieved a maximum operating frequency of 2 GHz, an area of 112 848 µm 2 (900 transistors), and consumed 15.47 mW of power operating at 2 GHz for an 8-bit design, which offers 252 different frequency divisions.

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Wide-division-range high-speed fully programmable frequency divider

Cited by 9 publications

References 10 publications

A 5–10-GHz Highly Configurable IEEE 802.15.4a/4z-Compatible IR-UWB Coherent Transmitter in 28-nm CMOS

A 5–10-GHz Highly Configurable IEEE 802.15.4a/4z-Compatible IR-UWB Coherent Transmitter in 28-nm CMOS

A novel topology for modular frequency dividers with enhanced speed and power efficiency

A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure

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