Spiking neural networks (SNN) provide a new computational paradigm capable of highly parallelized, real-time processing. Photonic devices are ideal for the design of high-bandwidth, parallel architectures matching the SNN computational paradigm. Furthermore, the co-integration of CMOS and photonic elements combineslow-loss photonic devices with analog electronics for greater flexibility of nonlinear computational elements. We designed and simulated an optoelectronic spiking neuron circuit on a monolithic silicon photonics (SiPh) process that replicates useful spiking behaviors beyond the leaky integrate-and-fire (LIF). Additionally, we explored two learning algorithms with the potential for on-chip learning using Mach-Zehnder Interferometric (MZI) meshes as synaptic interconnects. A variation of Random Backpropagation (RPB) was experimentally demonstrated on-chip and matched the performance of a standard linear regression on a simple classification task. In addition, we applied the Contrastive Hebbian Learning (CHL) rule to a simulated neural network composed of MZI meshes for a random input-output mapping task. The CHL-trained MZI network performed better than random guessing but did not match the performance of the ideal neural network (without the constraints imposed by the MZI meshes). Through these efforts, we demonstrate that co-integrated CMOS and SiPh technologies are well-suited to the design of scalable SNN computing architectures.
This letter presents an IEEE 802.15.4a/4z-compliant integrated impulse radio ultrawideband (IR-UWB) coherent transmitter that supports all channels in Band 2 from 6.5 to 10 GHz. A wideband phase-locked loop (PLL) with dual LC quadrature voltage-controlled oscillators (QVCOs) is implemented that covers more than 5-GHz frequency range. The PLL features a phase noise of −99.8 dBc/Hz at 1-MHz frequency offset and an rms jitter of 2.3 ps, which ensures reliable coherent operation. The quadrature clocks also make easy future I/ Q receiver integration. The pulse envelope and width are digitally controlled, thanks to our flexible digital pulseshaping configuration. Implemented in a 28-nm CMOS process with a supply voltage of 0.9 V, the chip occupies a core area of 0.21 mm 2 and supports channel 5-15 with a peak pulse repetition frequency (PRF) of 499.2 MHz. The transmitter has a maximum output swing of 430 mV and the power consumption is 1.3 nJ/pulse at a PRF of 15.6 MHz.
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