In this paper, we introduce a new topology for modular frequency dividers which improves the speed and decreases the power consumption in true-single-phaseclock (TSPC) based dividers and enhances the speed in their Extended-TSPC (E-TSPC) based counterparts. Two dividers are designed in 0.18 lm TSMC CMOS technology with 1.8 V supply voltage, to examine the speed and power efficiency of proposed structure. Post-layout simulation results reveal that in TSPC based design, use of proposed structure leads to about 38 % power reduction compared to the conventional topology. In addition, the E-TSPC based design achieves the speed as high as static dividers with maintaining the programmability and modularity of divider.
This paper presents a novel approach for anisochronous pulse-based modulation. In the proposed approach, referred to as the intertwined-pulse modulation (IPM), every pair of consecutive symbols overlap in time. This allows for shortening the time allocated for the transmission of the symbols, hence achieving temporal compaction while the data goes through the line encoding step in a digital communication system. The IPM is also uniquely superior to other existing anisochronous pulse-based modulation schemes in the fact that it exhibits robust symbol error rate against unwanted variations in both rise/fall times of the pulses in the modulated waveform, and in the threshold level used for data detection on the receiver side. An experimental setup was developed to implement an IPM encoder using standard digital hardware, and an IPM decoder as a part of the receiver system in software. According to the experimental results (supported by simulation results and theoretical studies), for the data mean value of mid-full-scale range, the proposed IPM scheme exhibits a time-domain compaction rate of up to 209.2%.
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