A novel topology for modular frequency dividers with enhanced speed and power efficiency

Abstract

In this paper, we introduce a new topology for modular frequency dividers which improves the speed and decreases the power consumption in true-single-phaseclock (TSPC) based dividers and enhances the speed in their Extended-TSPC (E-TSPC) based counterparts. Two dividers are designed in 0.18 lm TSMC CMOS technology with 1.8 V supply voltage, to examine the speed and power efficiency of proposed structure. Post-layout simulation results reveal that in TSPC based design, use of proposed structure leads to about 38 % power reduction compared to the conventional topology. In addition, the E-TSPC based design achieves the speed as high as static dividers with maintaining the programmability and modularity of divider.

A modified pulse swallow frequency divider for fractional-N PLL

“…As a crucial component of the fractional-N frequency synthesizer, the frequency divider puts forward higher requirements. Therefore, a high operating speed and low power consumption fractional-N frequency divider are highly desired [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The working speed limitation of pulse swallow frequency divider is determined by the delay time of MC signal (τ MC ) [1,2,3,20,21,22,23,24,25,26].…”