When are transmission-line effects important for on-chip interconnections

Deutsch, A.; Kopcsay, G.V.; Restle, P.J.; Katopis, G.A.; Becker, W.D.; Smith, H.; Coteus, P.; Surovic, C.W.; Rubin, B.J.; Dunne, Rajiv; Gallo, Tom; Jenkins, K.A.; Terman, Lewis M.; Dennard, R.H.; Sai-Halasz, G.A.; Knebel, D.R.

doi:10.1109/ectc.1997.606248

Cited by 69 publications

(31 citation statements)

References 4 publications

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“…The analysis of on-chip repeatered electrical interconnects was discussed extensively by Bakoglu [98] for the case of lines. A central conclusion of the recent work [91]- [97] is that inductance and transmission-line effects are becoming quite significant for long lines on CMOS chips, where previously such lines could be effectively modeled as lines. Other electrical options for long lines on chips include adding layers of external lines by solder bonding an interposer of copper lines and polymer dielectric onto the chip, with these lines also typically being lines [99].…”

Section: B Scaling Of Interconnectsmentioning

confidence: 99%

“…There has been considerable recent work, for example, by Deutsch et al [91]- [96] and others [97], examining the effects of inductance, skin effect, and transmission-line effects in wiring on chips. The analysis of on-chip repeatered electrical interconnects was discussed extensively by Bakoglu [98] for the case of lines.…”

Section: B Scaling Of Interconnectsmentioning

confidence: 99%

“…To model the lines properly so that such "velocity of light" effects are automatically included requires adding in the effects of line inductance. The inclusion of inductance and consequent transmission line effects is discussed in [91]- [97], where simulations show more detailed behavior of the cross-over from to (a mixture of and ) and behavior. Here we take a relatively simplistic analytic approach to expose the trends and underlying physical regimes.…”

Section: Appendix Bandwidth and Delay Of Global On-chip Electrical Inmentioning

confidence: 99%

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Rationale and challenges for optical interconnects to electronic chips

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Section: B Scaling Of Interconnectsmentioning

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Section: B Scaling Of Interconnectsmentioning

confidence: 99%

Section: Appendix Bandwidth and Delay Of Global On-chip Electrical Inmentioning

confidence: 99%

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2000

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“…But, with the recognized significance of including inductive effects and their impact on performance and signal integrity, several techniques have been proposed to deal with these effects. The most common of these techniques are: shielding [10] where signal lines are interdigitated with Vdd or ground alternatively in order to provide isolation of signal lines from their neighboring signals, and buffer insertion [11] where Manuscript received December 30, 2001; revised April 19, 2002. This work was supported by the Advanced Technology Group at Synopsys, the Somerset design center of Motorola, the DARPA packaging program, and the semiconductor research corporation.…”

mentioning

confidence: 99%

Expression of Concern: Managing on-chip inductive effects

Massoud

Majors²,

Kawa

et al. 2002

IEEE Trans. VLSI Syst.

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Abstract-With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

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“…Deutsch et al provided detailed conditional expressions to determine when distributed interconnect effects (usually modeled as transmission lines) are important for on-chip interconnects [3]. Consider a point to point net with length l, characteristic impedance Z 0 , resistance, capacitance and inductance per unit length R, C and L, total capacitance C T , and driven by a source impedance Z drv .…”

Section: Introductionmentioning

confidence: 99%

A new multi-ramp driver model with RLC interconnect load

Vakati

Wang

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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As the feature size is scaled down to 90 nm and below, fundamental modeling changes, such as the nonlinearity and higher frequencies of signals, require driver-load models to take into account propagation delay and slew rates. The conventional single Ceff (one-ramp) with lumped RC model is no longer accurate. In this paper we propose a new multi-ramp model with general RLC interconnects as loads. This new model accurately predicts both the 50% delay and the overall output waveform shape with inductance effects.

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When are transmission-line effects important for on-chip interconnections

Cited by 69 publications

References 4 publications

Rationale and challenges for optical interconnects to electronic chips

Rationale and challenges for optical interconnects to electronic chips

Expression of Concern: Managing on-chip inductive effects

A new multi-ramp driver model with RLC interconnect load

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