Expression of Concern: Managing on-chip inductive effects

Abstract

Abstract-With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

“…Consequently, the primary noise mitigation techniques, in addition to shield lines, modify layout properties such as the line width and spacing between adjacent lines. Capacitive and inductive coupling noise typically exhibits different and sometimes contradictory layout dependencies [13]- [14], which directly affect the noise mitigation techniques for capacitive coupling, inductive coupling, and simultaneous capacitive and inductive coupling. To better understand the dependence of each coupling effect on the layout parameters, the line parameters as a function of line width and spacing are examined, as illustrated in Fig.…”

“…Widening the lines should be considered only if the inductive coupling is negligible, since while the capacitive coupling noise will decrease, the inductive coupling noise will increase. However, if inductive coupling is dominant, increasing the space between the lines will have a negligible effect on the noise and the lines should be made more narrow [14]. Dominant capacitive coupling is expected between narrow and close lines since the small distance between the lines increases the coupling capacitance, and a narrow width results in high resistivity which decreases the inductive effects.…”

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

“…In [5] and [12] the authors suggested inter-digitating ground traces amongst the signal wires to reduce the routing resources needed for the shielding. The authors concluded that this technique would produce the highest reduction in inductance compared to the other techniques investigated.…”

Fault detection and isolation techniques for quasi delay-insensitive circuits

“…Although crosstalk is somewhat of a design issue, newer technologies have upwards of six metal layers and it can be difficult to guarantee that crosstalk faults won't occur. Inductive coupling is particularly challenging since it decays logarithmically with wire spacing [12], rather than linearly like capacitive coupling does. Transient faults due to radiation occur when a particle strikes some region of a device and creates a track of electron-hole pairs.…”