Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Vishnyakov, V.V.; Friedman, Eby G.; Kolodny, Avinoam

doi:10.1016/j.mejo.2011.12.007

Cited by 3 publications

(1 citation statement)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Power and ground noise is caused by high-frequency switching of the instantaneous current, which introduces large current spikes that IR and inductive (Ldi /dt) voltage drops, producing voltage fluctuations in the power and ground distribution networks [33], [43]- [46]. Interconnect noise [47]- [49] or crosstalk is the voltage change induced on a victim node due to capacitive or inductive coupling from a switching node. CMOS digital circuits are traditionally considered tolerant to noise due to the high-noise margins [42].…”

Section: A Signal Integrity Challenges In Deeply Scaled Cmosmentioning

confidence: 99%

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Bai

Song

Bojnordi

et al. 2016

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.Index Terms-Architecture-circuit codesign, energy efficient, low noise, microprocessors, MOS current-mode logic (MCML). 1063-8210

show abstract