VLSI Architecture &amp;amp; Implementation of H.264 Integer Transform

Raja, Gulistan; Khan, Shaheen; Mirza, M.J.

doi:10.1109/icm.2005.1590071

Cited by 8 publications

(5 citation statements)

References 4 publications

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“…This architecture required 13.28% lesser number of gates compared to the architecture proposed in [6]. Speed of our architecture is lesser than that in [6]. However this can be overcome by employing parallel architecture.…”

Section: Simulation and Synthesis Resultsmentioning

confidence: 83%

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

Korah

Perinbam

2008

J Sign Process Syst Sign Image Video Technol

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This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4× 4 integer transform, which is derived from the 4×4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture outperforms many recent implementations in terms of gate count and is capable of processing a 4×4 residual block in 4 clock cycles.

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Section: Simulation and Synthesis Resultsmentioning

confidence: 83%

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

Korah

Perinbam

2008

J Sign Process Syst Sign Image Video Technol

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“…The quantization parameters will be set and calculated in the quantization pre-process. To increase the computational efficiency of the texture architecture, the texture encoding process can be separated into two computational pipelined phases (Raja et al, 2005). Fig.…”

Section: Texture Architecture For Transform and Quantizationmentioning

confidence: 99%

“…In recent years, there have been many researchers who designed and developed integer transforms and quantization for the H.264 video coding (Kordasiewicz and Shirani, 2005;Fan, 2006;Fan and Cheng, 2005;Raja et al, 2005;Lin et al, 2005;Kordasiewicz and Shirani, 2004;Qian et al, 2006;Malvar et al, 2003;Wien, 2003;Liu et al, 2004;Wang et al, 2004;Zeng et al, 2001;Cheng et al, 2004;Madisetti and Willson, 1995;Chen et al, 2006). Downloaded by [University of Chicago Library] at 00:58 17 November 2014…”

Section: Introductionmentioning

confidence: 97%

FPGA implementations of low latency and high throughput 4×4 block texture coding processor for H.264/AVC

Fan¹,

Cheng

2009

Journal of the Chinese Institute of Engineers

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In this paper, low latency and high throughput texture coding architectures are proposed to realize the 4×4 integer/Hadamard transforms, the quantization (Q), and the inverse-quantization (IQ) schemes for the H.264/AVC application. Based on matrix operations, the efficient fast two-dimensional (2-D) 4×4 transforms can be derived from the proposed one-dimensional (1-D) fast 4×4 transforms through matrix decompositions. The fast 2-D 4×4 transform designs with the hardware sharing architecture can achieve high throughput and only need one clock cycle latency delay. The proposed cost-effective and hardware sharing fast 2-D 4×4 transform scheme doesn't require the transpose memory and can be applied to the 4CIF 4:2:0 video encoding. The hardware sharing architecture for both of the Q and the IQ is also developed for the low-cost application. With Xilinx FPGA verifications, the proposed low-cost 4×4 texture coding scheme, which can be applied to the CIF 4:2:0 30 frames/sec video encoding, can process up to 84 MHz with 90 k gate counts. Then the proposed high speed 4×4 texture coding design, which can be applied to the 4CIF 4:2:0 30 frames/ sec video encoding, can process up to 99 MHz with 135 k gate counts. Both of the two proposed texture coding architectures only require 4 clock cycles latency delay which is smaller than the traditional row-column architectures do.

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“…Different works have been published on the integer transform [15][16][17][18][19]. It is obvious that "I" shown in (1) or "H" shown in (12) can be implemented by a 1-D transform.…”

Section: Ict and Ht Architecturesmentioning

confidence: 99%

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Loukil¹,

Werda²,

Nouri³

et al. 2010

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In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

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VLSI Architecture & Implementation of H.264 Integer Transform

Cited by 8 publications

References 4 publications

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

FPGA implementations of low latency and high throughput 4×4 block texture coding processor for H.264/AVC

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

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VLSI Architecture &amp; Implementation of H.264 Integer Transform

Cited by 8 publications

References 4 publications

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

FPGA implementations of low latency and high throughput 4×4 block texture coding processor for H.264/AVC

FPGA Design of an Intra 16 &#215; 16 Module for H.264/AVC Video Encoder

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VLSI Architecture & Implementation of H.264 Integer Transform

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder