FPGA implementations of low latency and high throughput 4×4 block texture coding processor for H.264/AVC

Abstract

In this paper, low latency and high throughput texture coding architectures are proposed to realize the 4×4 integer/Hadamard transforms, the quantization (Q), and the inverse-quantization (IQ) schemes for the H.264/AVC application. Based on matrix operations, the efficient fast two-dimensional (2-D) 4×4 transforms can be derived from the proposed one-dimensional (1-D) fast 4×4 transforms through matrix decompositions. The fast 2-D 4×4 transform designs with the hardware sharing architecture can achieve high throughput and only need one clock cycle latency delay. The proposed cost-effective and hardware sharing fast 2-D 4×4 transform scheme doesn't require the transpose memory and can be applied to the 4CIF 4:2:0 video encoding. The hardware sharing architecture for both of the Q and the IQ is also developed for the low-cost application. With Xilinx FPGA verifications, the proposed low-cost 4×4 texture coding scheme, which can be applied to the CIF 4:2:0 30 frames/sec video encoding, can process up to 84 MHz with 90 k gate counts. Then the proposed high speed 4×4 texture coding design, which can be applied to the 4CIF 4:2:0 30 frames/ sec video encoding, can process up to 99 MHz with 135 k gate counts. Both of the two proposed texture coding architectures only require 4 clock cycles latency delay which is smaller than the traditional row-column architectures do.

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

“…The 8x8 transform and quantization for H.264 is presented in [20] and [21]. Several other designs based on H.264 codec have been reported in [22][23][24][25][26][27]. The authors in [28] present a design for the quantization for AVS.…”

“…The quantization unit has four identical sub-quantizers. The design presented in [27] can support only one standard, H.264 and the implementation is quite straight forward, and hence has less hardware than ours. However none of these designs can support the entire six quantization scheme.…”

Division-Free Multiquantization Scheme for Modern Video Codecs

“…In Table 4, we compare the performance (FPGA only) of this combined multi-DCT and multiquantizer with the existing designs; those include both DCT and quantization block. The designs in [6] and [10] can support only one standard, H.264, and hence has lesser hardware than ours. Compared to the existing designs, our design has higher frequency of operation with comparable hardware count.…”

“…The 8 × 8 transform and quantization for H.264 is presented in [3] and [4]. Several other designs based on H.264 codec have been reported in [5][6][7][8][9][10]. The authors in [11] present a design for the quantization for AVS.…”

An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs

“…Previous works have already been successes in hardware implementation of transforms and quantization. Chih-Peng Fan and Yu-Lin Cheng [11] proposed a design with a high through-put and low latency architecture using Canonical Signed Digit (CSD) multiplier for shared quantization/inverse-quantization. In [12], Yu-Ting Kuo presented an area-efficient architecture using direct 2-D transform method.…”