FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Abstract

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

Performance evaluation of a new efficient H.264 intraprediction scheme

“…The results show that the proposed prediction technique enhances the compression ratio and the PSNR for the two HD videos. Seeking for a much more accurate judgment of the proposed prediction technique, we compared it with the hardware implementations of Bharathi and Nagabhushana [3], which used the Lena CIF video, and Loukil et al [25], which used the Foreman CIF video, as shown in Table 5. The comparison is performed in terms of PSNR only as the considered papers for comparison did not include information about compression ratio or bit rate.…”