FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

Abstract

This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4× 4 integer transform, which is derived from the 4×4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture outperforms many recent implementations in terms of gate count and is capable of processing a 4×4 residual block in 4 clock cycles.

Efficient hardware solution for practical intra h.264/SVC video encoder implementation

“…For this experiment the target device was a Xilinx XC2VP30). In other to compose a multi-encoder solution, it was selected two works, which have been designed to support efficiently a HD single layer application [12] [13]. Each work optimizes one path of the H.264 intra computation coding (forward or inverse respectively).…”

Hardware integrated quantization solution for improvement of computational H.264 encoder module

“…The first one (called BASIC) presents low complexity and a performance compatible with others solutions like the work of Korah [13]. By duplicating the Quantization module we can produce a solution two times faster (called DUAL), which results in a global complexity increasing of only 45%.…”

A new VLSI architecture for 3D-DCT video compression system

“…Each DCT is processed independently. In case of spatial domain, we use the integer transform developed for H.264 [14] and [16]. Hardware implementation of integer transform is very simple by using shifts, adders, and muxes without any multiplier [16].…”

“…Scaling and quantization in spatial domain : Each transformed pixel from 2D-DCT output block goes to scaling and quantization block in scan order. As mentioned above, we^d also use the same algorithm as H.264 [14] and choose architecture [16] developed and confirmed for H.264. It takes three cycles to scale and quantize each transformed pixel based on [16].…”

“…As mentioned above, we^d also use the same algorithm as H.264 [14] and choose architecture [16] developed and confirmed for H.264. It takes three cycles to scale and quantize each transformed pixel based on [16]. Significant difference from the baseline architecture is that early compression in spatial domain.…”